Top Design Engineer Jobs in Singapore

Develop production Python software and C++ integrations for photonic integrated circuit design. Build connectors to EDA tools, automate layout, simulation, verification, and foundry workflows, and create agentic AI features. Apply photonics and physics expertise to workflows involving component and circuit simulation, compact modeling, PDKs, and fabrication-aware pipelines using GPU-accelerated solvers. Collaborate with users on quantum, RF, silicon photonics, and co-packaged optics applications.

Validate HBM design and test modes through simulation, lab and ATE analysis, root-cause manufacturing/test issues, collaborate with design, manufacturing, test and quality teams, document architecture per JEDEC, and apply data analysis and AI-enabled improvements to improve product reliability and performance.

As a Senior Engineer in NAND Silicon Design Validation, you'll develop and validate NAND Flash products, perform simulations, and collaborate across teams to address design issues.

Performs design validation for High Bandwidth Memory products through simulation, data analysis, ATE and laboratory debugging. Collaborates with design, manufacturing, test, quality, process engineering, and customers to resolve hardware and software issues. Analyzes validation data, assesses product risks, documents architecture, and applies knowledge of JEDEC HBM specifications, schematics, layouts, VLSI, and semiconductor processes. Contributes to innovation and AI-enabled process improvements.

Lead design validation for HBM products across design, manufacturing, test, quality, and customer teams. Define validation strategies, execute simulation and ATE/bench analysis, investigate complex silicon and manufacturing issues, perform root-cause analysis, assess risks using statistical methods, and develop automated data-analysis solutions. The role also requires deep understanding of memory architecture, JEDEC specifications, semiconductor processes, device physics, and validation methodologies.

Performs design and test-mode validation for High Bandwidth Memory products using simulation, data analysis, ATE and bench analysis. Debugs manufacturing, test and quality issues through hardware and software troubleshooting, circuit simulations and lab work. Collaborates with design, manufacturing, test, quality, PE teams and customers. Applies JEDEC specifications, schematic and layout knowledge, statistical validation tools, and AI-enabled improvements to support product reliability and continuous innovation.

Develops and supports optical wafer inspection tools by resolving front-end issues, creating system specifications and test methods, reviewing design changes, preparing engineering documentation, and supporting field escalations and beta testing. The role requires troubleshooting, experimentation, data analysis, technical drawing and BOM interpretation, and collaboration with development engineering teams. Travel of up to 25% is expected.

Design and implement large-scale integrated circuits using commercial and in-house EDA tools across advanced 7nm to 2nm process technologies. Manage complete RTL-to-GDS or gates-to-GDS implementation flows, including placement, clock tree synthesis, routing, physical and formal verification, and timing analysis. Apply UNIX/Linux and Tcl or Bash scripting, with front-end design and synthesis knowledge beneficial.

Lead physical design implementation for large, high-performance ASICs using advanced 5nm, 3nm, and 2nm processes. Apply commercial and internal EDA tools, resolve timing violations with RTL and physical design teams, support customers, manage technical relationships, and develop innovative design flows for computing and networking products.

Design and implement large-scale integrated circuits using commercial and in-house EDA tools across advanced 7nm to 2nm process technologies. Manage complete RTL-to-GDS or gates-to-GDS flows, including placement, clock tree synthesis, routing, physical and formal verification, and timing analysis. Apply UNIX/Linux and scripting skills in Tcl, Bash, and Python. A degree in electrical, electronics, or computer engineering and at least five years of relevant experience are required.

Design and implement large-scale ASICs from RTL or gates through GDS using commercial and in-house EDA tools. Responsibilities include synthesis, placement, clock tree synthesis, routing, physical and formal verification, and timing analysis for advanced-node 7nm to 2nm integrated circuits. GPU, CPU, or DSP architecture knowledge and UNIX/Linux scripting experience are advantageous.

Design and implement large-scale integrated circuits using commercial and in-house EDA tools across advanced 7nm to 2nm process technologies. Manage complete RTL-to-GDS or gates-to-GDS flows, including placement, clock tree synthesis, routing, physical and formal verification, and timing analysis. The role also involves UNIX/Linux and Tcl/Bash scripting, with front-end design and synthesis knowledge preferred.

Design and implement large-scale ASICs using commercial and in-house EDA tools across advanced 7nm to 2nm process technologies. Manage complete RTL-to-GDS or gates-to-GDS flows, including synthesis, placement, clock tree synthesis, routing, physical and formal verification, and timing analysis. Knowledge of GPU, CPU, or DSP architectures, UNIX/Linux, and scripting is advantageous.

Owns advanced package architecture and execution from feasibility through tape-out, qualification, and production readiness. Leads complex package trade-offs across silicon, technology, assembly, quality, suppliers, and OSAT teams. Integrates electrical, thermal, mechanical, power, signal, and manufacturing requirements in silicon-package-board co-design. Advances design rules, automation workflows, and technology roadmaps while mentoring engineers and serving as the technical authority for package design decisions.

Design and validate high-speed digital hardware for networking platforms. Responsibilities include component selection, schematic design, board bring-up, debugging, lab measurements, testing, feasibility studies, design margin analysis, root-cause analysis, and collaboration with global engineering teams. The role provides mentorship and hands-on experience for recent graduates developing real-world networking products.

Leads power architecture and board-level power design for advanced networking platforms. Designs AC-DC and DC-DC conversion, regulators, hot-swap and protection circuits, sequencing, monitoring, and power distribution systems. Owns simulation, schematic development, bring-up, validation, compliance testing, characterization, and root-cause investigations. Establishes design standards, drives system-level trade-offs, collaborates across engineering and manufacturing teams, and mentors senior engineers.

Leads complex hardware designs for next-generation networking platforms across component selection, schematic capture, board architecture, bring-up, debugging, validation, and production readiness. Drives high-speed digital design decisions involving signal integrity, power distribution, performance, reliability, and system-level trade-offs. Collaborates with layout, validation, manufacturing, and firmware teams, performs root-cause analysis and empirical testing, establishes design best practices, and mentors junior engineers.

Design mechanical systems and custom machinery for high-power-density power electronics, from concept through production, installation, commissioning, and handover. Responsibilities include CAD modeling, structural and thermal analysis, packaging, validation testing, GD&T drawings, PLM documentation, supplier collaboration, prototype development, root-cause analysis, cooling-system design, manufacturing support, FMEA, and reliability activities. The role requires close collaboration with electrical, controls, manufacturing, quality, and test teams and includes up to 20% international travel.

Lead end-to-end hardware architecture for high-performance networking platforms across multiple product generations. Define system and board-level architectures, make trade-offs across silicon, memory, interfaces, power, timing, thermal, firmware, and manufacturing, and guide feasibility, modeling, validation, reviews, and production. Establish reusable design standards, influence global engineering teams, resolve complex technical issues, and mentor senior engineers and future architects.

Design and build interfaces across HUD’s AI data platform and marketplace. Translate complex agent runs, evaluation results, reward signals, and reinforcement learning workflows into clear, actionable products. Partner with users, researchers, and engineers; conduct user research; ship and refine experiences; establish reusable interaction patterns; and maintain high standards for usability, visual quality, and implementation.

Develop optical control ICs for AI datacenter applications. Responsibilities include defining digital architectures, designing and implementing block- and chip-level RTL, translating algorithms into digital signal-processing blocks, and contributing to digital and mixed-signal verification and testbench development. The role collaborates with analog, mixed-signal, and system teams to deliver complex SoC designs.

Lead advanced semiconductor packaging thermal-mechanical FEA projects, developing and validating high-fidelity models for reliability, stress, warpage, fatigue, creep, delamination, and process effects. Translate cross-functional engineering questions into simulation plans, perform sensitivity and optimization studies, correlate models with testing and metrology, and deliver design recommendations. The role also includes owning workflows, mentoring engineers, establishing modeling standards, supporting technology roadmaps, and evaluating emerging packaging materials, processes, and architectures.

Design and advance manufacturing solutions for advanced semiconductor inspection and metrology products. Collaborate with manufacturing, supply chain, installation, quality, global suppliers, and design engineering teams to develop scalable, efficient, and cost-effective electronics manufacturing processes and products.

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G. Responsibilities include package layout and routing, high-speed SerDes and RF structures, impedance matching, signal and power integrity, thermal management, manufacturability, reliability, and coordinating multiple projects with global teams and external vendors.

The role involves leading design projects for commuter and road infrastructure, conducting feasibility studies, and managing consultancy contracts while collaborating with stakeholders on developing user-friendly transport solutions.