Top Design Engineer Jobs in Singapore

Leads specification, architecture, transistor-level design, verification, layout supervision, validation, and manufacturing test for complex analog IC subsystems. Partners with architecture, RTL, product, applications, and marketing teams; resolves cross-block issues; supports customer and manufacturing challenges; and mentors senior engineers without formal management responsibility.

Leads the analog design organization and sets architecture, specifications, methodology, and technical direction across multiple semiconductor programs. Directly designs or supervises critical transistor-level analog blocks, oversees verification, validation, layout, and production bring-up, and resolves high-risk technical issues. The role also mentors and manages engineers, chairs design reviews, partners with digital and product teams, supports customer and executive discussions, and drives improvements in tools, design flow, and IP reuse.

Lead system and subsystem integration, testing, characterization, and specification activities for semiconductor inspection systems. Define architectures, create test plans, resolve complex optical-mechanical and system issues, and support manufacturing and field service teams. Deliver technical training, maintain documentation, coordinate cross-functional projects, report progress and risks, and contribute to product strategy and roadmap alignment. Requires an advanced technical degree and preferably more than three years of relevant experience, with up to 20% international travel.

Manage optical alignment equipment and methodologies for wafer inspection tools, improve optical integration yield and predictability, troubleshoot manufacturing issues, resolve supplier quality problems, support quality and purchasing improvements, and ensure manufacturing readiness through design reviews.

Supports manufacturing, integration, and sustaining of electronic subsystems and assemblies. Troubleshoots PCB, wiring, and system-level issues; performs root-cause analysis; implements corrective actions; improves yield, reliability, quality, and cost; develops manufacturing documentation; supports validation and qualification testing; resolves supplier issues; and manages engineering changes across the product lifecycle.

Supports production builds, system integration, manufacturing ramp, and sustaining engineering for electrical systems. Troubleshoots electronic and system-level issues, performs root cause analysis, implements corrective actions, and develops manufacturing documentation. Collaborates with design, quality, supply chain, suppliers, and contract manufacturers. Supports validation, qualification, reliability testing, engineering changes, yield improvement, cost reduction, and continuous improvement initiatives.

Lead physical design and implementation for complex SoC and SerDes/interconnect designs from RTL through GDSII tapeout. Responsibilities include floorplanning, power and clock planning, place-and-route, PPA optimization, timing, power, noise, EM/IR-drop analysis, physical verification, signoff, IP integration, flow automation, and methodology development.

As a Senior Engineer in NAND Silicon Design Validation, you'll develop and validate NAND Flash products, perform simulations, and collaborate across teams to address design issues.

Define physical design rules for Non-Volatile Memory technologies, interact with process integration, evaluate design feasibility, and support design rule checking.

Integrate and customize a commercial RISC-V core soft IP, perform RTL (Verilog/SystemVerilog) front-end and control-path modifications, tailor microarchitecture for PPA, support ASIC front-end tasks (synthesis, STA, power, floorplanning), collaborate across performance/middle-end/back-end teams, and contribute to pre- and post-silicon verification and debugging.

Lead end-to-end physical implementation of high-speed PCIe controller and PHY blocks from netlist to GDSII. Perform floorplanning, placement, CTS, routing, STA, timing closure across PVT corners, power integrity (IR/EM) analysis, DRC/LVS/ERC signoff with Calibre, and tapeout support. Collaborate with RTL, synthesis, DFT, and verification teams and contribute to PD methodology and automation scripting.

Lead mechanical design for consumer electromechanical products from concept through production. Responsibilities include CAD modeling, prototyping, testing, thermal/fluid/structural analysis, cross-functional collaboration, DFM/DFA, tolerance analysis, and manufacturing ramp support in Asia. The role requires designing plastic, metal, and soft goods components integrated with sensors and actuators, supporting high-volume manufacturing, and traveling to China as needed.

Develop, validate, and qualify NAND Flash memory products across pre-silicon and post-silicon stages. Responsibilities include Verilog simulations, Cadence and CAD tool use, circuit analysis, electrical failure analysis, device characterization, configuration validation, engineering sample support, and troubleshooting with cross-functional R&D, manufacturing, quality, and business teams. The role also incorporates AI-assisted engineering tools and continuous improvement initiatives.

Validate and qualify NAND flash products across pre-silicon and post-silicon stages. Perform simulations with CAD and Verilog, run device characterization and failure analysis, define product configurations, support engineering sample prep, and integrate AI-assisted tools to improve workflows while collaborating cross-functionally to resolve design issues.

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G. Responsibilities include package layout and routing, high-speed SerDes and RF structures, impedance matching, signal and power integrity, thermal management, manufacturability, reliability, and coordinating multiple projects with global teams and external vendors.

Design and optimize ultra-low-power embedded SRAM and register file IPs, develop/enhance SRAM compilers, implement memory peripheral circuits, perform timing/power/low-voltage characterization, correlate silicon measurements, drive yield improvements, build automation scripts, and support IP integration through production.

Manage optical alignment equipment and methodologies for semiconductor wafer inspection tools. Improve optical integration yield and predictability, troubleshoot manufacturing issues, coordinate supplier quality improvements, and support cost reductions. The role requires hands-on assembly, alignment, calibration, integration, and testing of opto-mechanical systems, plus manufacturing procedure development, team leadership, problem solving, and 25% international travel.

Manage optical alignment equipment and methodologies for semiconductor wafer inspection tools. Improve optical integration yield and predictability, troubleshoot manufacturing issues, resolve supplier quality problems, support cost reduction initiatives, participate in design reviews, and ensure product manufacturing readiness. The role also develops manufacturing procedures and leads teams assembling, aligning, calibrating, and testing opto-mechanical systems.

Develop and integrate optical wafer inspection systems for semiconductor manufacturing. Responsibilities include defining system specifications, supporting product development and design changes, resolving field customer issues, creating documentation and engineering change orders, developing test methods, analyzing technical problems, and supporting beta testing. The role requires engineering expertise across optical, mechanical, electrical, and software components and up to 30% travel.

Manage optical alignment equipment and methodologies for semiconductor wafer inspection tools. Improve mechanical-part yield and process predictability, integrate and troubleshoot mechanical systems, resolve supplier quality issues, and support quality improvements and cost reductions. Develop manufacturing procedures and lead assembly teams for optical mechanical systems. The role requires hands-on assembly, alignment, calibration, integration, testing, project management, and 25% travel.

Manage optical alignment equipment and methodologies for wafer inspection tools. Improve optical integration yield and predictability, troubleshoot manufacturing issues, resolve supplier quality problems, support cost reductions, and ensure manufacturing readiness through design reviews. Lead assembly, alignment, calibration, testing, and manufacturing procedure development for opto-mechanical systems.

Manage optical alignment equipment and methodologies for wafer inspection tools, improve mechanical component yield and predictability, troubleshoot manufacturing integration issues, resolve supplier quality problems, and support quality and purchasing initiatives. The role also develops manufacturing procedures, leads optical-mechanical assembly teams, and requires hands-on experience with assembly, alignment, calibration, integration, and testing.

Owns the technical and quality performance of electronic subassemblies, resolves production and customer issues, conducts failure analysis, improves supplier quality and manufacturing yields, and supports ECOs, testing, cost reduction, transfers, and new product introduction. The role collaborates with design and manufacturing teams on DFM/DFT compliance, production readiness, ramp-up, and supplier training. Travel of up to 25% is required.

Implement ISP algorithms in hardware using Verilog, SystemVerilog, or SystemC; define architectures based on product and performance requirements; estimate gate count and power; verify ISP and digital-system logic; optimize designs for efficiency; and collaborate with ISP algorithm teams.

Design and develop NPU microarchitectures from system requirements, including RTL coding in Verilog/SystemVerilog, performance modeling, and PPA optimization. Collaborate with verification, software, compiler, and toolchain teams; resolve lint, timing, CDC, and integration issues; support testing and debugging; and produce design documentation. The role requires completed NPU design experience, substantial digital and SoC design expertise, and may involve leading a small engineering team.