Top Design Engineer Jobs in Singapore

Manage optical alignment equipment and methodologies for semiconductor wafer inspection tools. Improve optical integration yield and predictability, troubleshoot manufacturing issues, resolve supplier quality problems, support cost reduction initiatives, participate in design reviews, and ensure product manufacturing readiness. The role also develops manufacturing procedures and leads teams assembling, aligning, calibrating, and testing opto-mechanical systems.

Manage optical alignment equipment and methodologies for semiconductor wafer inspection tools. Improve mechanical-part yield and process predictability, integrate and troubleshoot mechanical systems, resolve supplier quality issues, and support quality improvements and cost reductions. Develop manufacturing procedures and lead assembly teams for optical mechanical systems. The role requires hands-on assembly, alignment, calibration, integration, testing, project management, and 25% travel.

Develop and integrate optical wafer inspection systems for semiconductor manufacturing. Responsibilities include defining system specifications, supporting product development and design changes, resolving field customer issues, creating documentation and engineering change orders, developing test methods, analyzing technical problems, and supporting beta testing. The role requires engineering expertise across optical, mechanical, electrical, and software components and up to 30% travel.

Manage optical alignment equipment and methodologies for wafer inspection tools. Improve optical integration yield and predictability, troubleshoot manufacturing issues, resolve supplier quality problems, support cost reductions, and ensure manufacturing readiness through design reviews. Lead assembly, alignment, calibration, testing, and manufacturing procedure development for opto-mechanical systems.

Manage optical alignment equipment and methodologies for wafer inspection tools, improve mechanical component yield and predictability, troubleshoot manufacturing integration issues, resolve supplier quality problems, and support quality and purchasing initiatives. The role also develops manufacturing procedures, leads optical-mechanical assembly teams, and requires hands-on experience with assembly, alignment, calibration, integration, and testing.

Owns the technical and quality performance of electronic subassemblies, resolves production and customer issues, conducts failure analysis, improves supplier quality and manufacturing yields, and supports ECOs, testing, cost reduction, transfers, and new product introduction. The role collaborates with design and manufacturing teams on DFM/DFT compliance, production readiness, ramp-up, and supplier training. Travel of up to 25% is required.

Develops and executes verification plans for SoC, IP, and mixed-signal designs. Builds SystemVerilog/UVM testbenches, creates directed and constrained-random tests, drives coverage closure, develops assertions, analyzes regressions, and debugs RTL across simulation and emulation. Collaborates with architecture, design, firmware, and validation teams; improves automation and CI flows; supports pre- and post-silicon debugging; and mentors junior engineers.

Design and build interfaces for HUD’s AI agent training, evaluation, and marketplace products. Translate complex reinforcement learning workflows, agent runs, evaluation results, reward signals, and quality feedback into clear, actionable experiences. Collaborate with users, researchers, and engineers to ship polished products, conduct user discovery, improve usability, and develop reusable interaction patterns.

Implement ISP algorithms in hardware using Verilog, SystemVerilog, or SystemC; define architectures based on product and performance requirements; estimate gate count and power; verify ISP and digital-system logic; optimize designs for efficiency; and collaborate with ISP algorithm teams.

Design and develop NPU microarchitectures from system requirements, including RTL coding in Verilog/SystemVerilog, performance modeling, and PPA optimization. Collaborate with verification, software, compiler, and toolchain teams; resolve lint, timing, CDC, and integration issues; support testing and debugging; and produce design documentation. The role requires completed NPU design experience, substantial digital and SoC design expertise, and may involve leading a small engineering team.

Implements ISP algorithms in hardware using Verilog, SystemVerilog, or SystemC. Verifies logic at ISP and digital-system levels, optimizes designs for gate count and power consumption, and collaborates with ISP algorithm teams. Requires an engineering degree, RTL and verification knowledge, C/C++ programming experience, strong debugging skills, communication abilities, adaptability, and results orientation. SystemC with high-level synthesis experience and CMOS image sensor knowledge are preferred.

Designs and architects digital SoC platforms for video processing, neural processing, and camera analytics. Responsibilities include defining SoC architectures, developing RTL in Verilog/SystemVerilog, measuring power, timing, and area, and supporting comprehensive verification through successful silicon implementation. The role also involves processor-system integration, embedded C and assembly programming, scripting, system modeling, simulation, and cross-functional collaboration.

Design and verify CMOS I/O and analog/mixed-signal circuits, including references, op-amps, comparators, and power-on-reset circuits. Run AC/DC, signal integrity, jitter, power, reliability, and EMIR analyses. Collaborate with layout teams, create Verilog, Liberty, and IBIS models, document designs, and support chip integration and silicon bring-up. The role requires advanced-node CMOS expertise, knowledge of I/O protocols, and proficiency with Cadence Virtuoso and SPICE/Spectre simulation.

Lead verification of digital and mixed-signal SoC designs. Develop block, subsystem, and chip-level test plans; implement scalable UVM/SystemVerilog testbenches; write C-based SoC tests; apply power-aware CPF/UPF flows; automate randomized testing and scoreboards; debug, perform root-cause analysis, track coverage metrics, and collaborate with design and software teams to deliver chips to spec.

Leads end-to-end ATE test hardware development for wafer sort and final test, including architecture, schematic design, PCB layout, SI/PI analysis, validation, debugging, release, and production support. Partners with engineering, operations, quality, procurement, suppliers, and manufacturing teams to deliver high-performance hardware. Establishes design methodologies, manages technical risks and initiatives, mentors engineers, and drives supplier capability and continuous improvement across semiconductor test programs.

Build production-quality, pixel-accurate UI components and interactions in React Native; prototype in Figma with designers; own the design system and component library; improve performance, animations, and cross-platform UI architecture; define design-to-dev tooling and collaborate across design and engineering.

Design Engineer Intern will create end-to-end product surfaces for autonomous agents, build working prototypes in code, use AI tools, run lightweight user tests, maintain the design system, collaborate with engineers, and focus on interaction, motion, and fine UI craft.

Lead RTL design and verification for ASIC/SoC products, ensuring efficient designs and integration of IP blocks. Support Post-Si testing and mentor junior engineers.

Responsible for detailed design of digital circuits, SoC integration, verification using multiple methods, and documentation of requirements and designs.

Develop digital circuits and SoC for low-power MCU and wireless products, including design, integration, and verification tasks.

The Manufacturing Design Engineer will troubleshoot systems, analyze data, handle experiments, and design optical-based semiconductor inspection equipment while managing projects and collaborating with teams.

Validate HBM design and test modes through simulation, lab and ATE analysis, root-cause manufacturing/test issues, collaborate with design, manufacturing, test and quality teams, document architecture per JEDEC, and apply data analysis and AI-enabled improvements to improve product reliability and performance.

Perform hull, machinery and outfitting design reviews for newbuild vessels; revise GA, structural and system drawings; conduct feasibility studies for equipment and arrangements; ensure compliance with IMO regulations; verify basic, detailed and production designs; liaise with designers, classification society and procure hull, outfitting, machinery and ancillaries.

Responsible for end-to-end FPGA development, including design, simulation, validation, and integration with hardware, as well as collaboration on system testing.

The role involves interfacing with design engineering for new product releases, enhancing designs, troubleshooting, and conducting failure analyses while supporting manufacturing processes.