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Silicon Labs

Design Verification Engineer II

Posted One Month Ago
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Hybrid
Singapore, SGP
Senior level
Hybrid
Singapore, SGP
Senior level
Develops and executes verification plans for SoC, IP, and mixed-signal designs. Builds SystemVerilog/UVM testbenches, creates directed and constrained-random tests, drives coverage closure, develops assertions, analyzes regressions, and debugs RTL across simulation and emulation. Collaborates with architecture, design, firmware, and validation teams; improves automation and CI flows; supports pre- and post-silicon debugging; and mentors junior engineers.
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Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

About the team

The IoT Digital Design team is a state-of-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification, design, verification, emulation, and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best in class radios to support a wide range of wireless IoT applications and standards. We strive to provide best in class technology solutions through innovation in custom RISC-V Cores and AI/ML components. 


Responsibilities

  • Develop and execute verification plans for SoC/IP blocks and mixed-signal designs.
  • Build and maintain SystemVerilog/UVM-based testbenches.
  • Create directed and constrained-random test cases.
  • Drive functional coverage closure, assertions, and regression analysis.
  • Debug RTL and verification failures across simulation/emulation environments.

Collaborate closely with:

  • RTL designers
  • architecture teams
  • firmware/software teams
  • validation engineers
  • Improve verification methodologies, automation, and CI flows.
  • Support pre-silicon and occasionally post-silicon debug activities.
  • Mentor junior engineers and contribute to verification strategy.

Qualifications/Skills you'll need:

  • BS/MS in Electrical or Computer Engineering
  • 5–10+ years of verification experience

Experience with:

  • Wireless SoCs
  • MCU subsystems
  • AMBA/AXI/APB protocols
  • embedded systems
  • low-power IoT silicon

Technical Knowledge and Skill Requirements

  • SystemVerilog
  • UVM/OVM
  • RTL and GLS simulation/debug
  • Functional coverage
  • Assertions (SVA)
  • Python/Perl/TCL scripting
  • SoC/IP verification
  • Low-power verification concepts
  • CDC/RDC verification
  • Mixed signal / AMS verification 

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

  • Medical and dental insurance coverage including spouse and child(ren)
  • Bi yearly health screening and flu vaccination
  • Office location is above Tai Seng MRT station

#LI-Hybrid

#LI-DK1

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

Silicon Labs Singapore, Singapore, SGP Office

Singapore, Singapore

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