Top Design Jobs in Singapore

Leads specification, architecture, transistor-level design, verification, layout supervision, validation, and manufacturing test for complex analog IC subsystems. Partners with architecture, RTL, product, applications, and marketing teams; resolves cross-block issues; supports customer and manufacturing challenges; and mentors senior engineers without formal management responsibility.

Leads the analog design organization and sets architecture, specifications, methodology, and technical direction across multiple semiconductor programs. Directly designs or supervises critical transistor-level analog blocks, oversees verification, validation, layout, and production bring-up, and resolves high-risk technical issues. The role also mentors and manages engineers, chairs design reviews, partners with digital and product teams, supports customer and executive discussions, and drives improvements in tools, design flow, and IP reuse.

As a Senior Engineer in NAND Silicon Design Validation, you'll develop and validate NAND Flash products, perform simulations, and collaborate across teams to address design issues.

Define physical design rules for Non-Volatile Memory technologies, interact with process integration, evaluate design feasibility, and support design rule checking.

Develop, validate, and qualify NAND Flash memory products across pre-silicon and post-silicon stages. Responsibilities include Verilog simulations, Cadence and CAD tool use, circuit analysis, electrical failure analysis, device characterization, configuration validation, engineering sample support, and troubleshooting with cross-functional R&D, manufacturing, quality, and business teams. The role also incorporates AI-assisted engineering tools and continuous improvement initiatives.

Validate and qualify NAND flash products across pre-silicon and post-silicon stages. Perform simulations with CAD and Verilog, run device characterization and failure analysis, define product configurations, support engineering sample prep, and integrate AI-assisted tools to improve workflows while collaborating cross-functionally to resolve design issues.

The NAND Design Rule Manager leads a team in developing and producing advanced 3D NAND technologies, manages design rules and PDK deliverables, collaborates across technical teams for quality assurance, and drives continuous improvement in processes.

The Staff Engineer will lead validation work, collaborate across functions, resolve issues, promote innovation, and improve processes in semiconductor technology.

Lead verification of digital and mixed-signal SoC designs. Develop block, subsystem, and chip-level test plans; implement scalable UVM/SystemVerilog testbenches; write C-based SoC tests; apply power-aware CPF/UPF flows; automate randomized testing and scoreboards; debug, perform root-cause analysis, track coverage metrics, and collaborate with design and software teams to deliver chips to spec.

Manage engineering scope, schedule, and budget for multi-disciplinary datacenter design and construction projects across North-East Asia. Lead teams of architects and engineers from site due diligence through design, permitting, procurement, construction, and turnover. Oversee feasibility studies, compliance, contracts, and stakeholder coordination to deliver mission-critical datacenter infrastructure aligned to regional capacity roadmaps.

Manages creative and packaging design accounts from briefing through delivery, serving as the primary client liaison and coordinating internal creative and production teams. Responsibilities include project scheduling, budget and scope control, quality reviews, status reporting, capacity planning, invoicing support, profitability reporting, and identifying account growth opportunities. The role requires strong project management, branding knowledge, communication skills, and business-level Japanese and English proficiency. It is onsite in Tokyo.

The Staff Engineer leads analog and mixed-signal block design, conducts design reviews, mentors junior engineers, and develops methodologies for advanced technology applications.

Lead system and subsystem integration, testing, characterization, and specification activities for semiconductor inspection systems. Define architectures, create test plans, resolve complex optical-mechanical and system issues, and support manufacturing and field service teams. Deliver technical training, maintain documentation, coordinate cross-functional projects, report progress and risks, and contribute to product strategy and roadmap alignment. Requires an advanced technical degree and preferably more than three years of relevant experience, with up to 20% international travel.

Leads complex, high-value event and experiential projects from inception through delivery. Oversees client relationships, production teams, resources, budgets, timelines, logistics, risk, and commercial outcomes. Provides senior leadership, develops client opportunities, supports new business pitches, manages stakeholders, and ensures projects align with strategic objectives. The role also guides creative delivery, develops team members, and reports project performance and issues to senior leadership.

Leads end-to-end ATE test hardware development for wafer sort and final test, including architecture, schematic design, PCB layout, SI/PI analysis, validation, debugging, release, and production support. Partners with engineering, operations, quality, procurement, suppliers, and manufacturing teams to deliver high-performance hardware. Establishes design methodologies, manages technical risks and initiatives, mentors engineers, and drives supplier capability and continuous improvement across semiconductor test programs.

Manage optical alignment equipment and methodologies for wafer inspection tools, improve optical integration yield and predictability, troubleshoot manufacturing issues, resolve supplier quality problems, support quality and purchasing improvements, and ensure manufacturing readiness through design reviews.

Designs, sustains, debugs, and troubleshoots PCBs, power supplies, electronic test fixtures, and board-level subsystems. Performs failure analysis and root-cause investigations across analog, digital, and mixed-signal electronics. Supports engineering validation, manufacturing improvements, corrective actions, ECO execution, and technical documentation. Collaborates with vendors and global cross-functional teams while communicating technical findings, risks, and project status.

Supports manufacturing, integration, and sustaining of electronic subsystems and assemblies. Troubleshoots PCB, wiring, and system-level issues; performs root-cause analysis; implements corrective actions; improves yield, reliability, quality, and cost; develops manufacturing documentation; supports validation and qualification testing; resolves supplier issues; and manages engineering changes across the product lifecycle.

Supports production builds, system integration, manufacturing ramp, and sustaining engineering for electrical systems. Troubleshoots electronic and system-level issues, performs root cause analysis, implements corrective actions, and develops manufacturing documentation. Collaborates with design, quality, supply chain, suppliers, and contract manufacturers. Supports validation, qualification, reliability testing, engineering changes, yield improvement, cost reduction, and continuous improvement initiatives.

The role involves validating HBM designs through cross-functional collaboration, data analysis, and innovative problem-solving in a dynamic environment.

Lead physical design and implementation for complex SoC and SerDes/interconnect designs from RTL through GDSII tapeout. Responsibilities include floorplanning, power and clock planning, place-and-route, PPA optimization, timing, power, noise, EM/IR-drop analysis, physical verification, signoff, IP integration, flow automation, and methodology development.

Validate HBM design and test modes through simulation, lab and ATE analysis, root-cause manufacturing/test issues, collaborate with design, manufacturing, test and quality teams, document architecture per JEDEC, and apply data analysis and AI-enabled improvements to improve product reliability and performance.

Integrate and customize a commercial RISC-V core soft IP, perform RTL (Verilog/SystemVerilog) front-end and control-path modifications, tailor microarchitecture for PPA, support ASIC front-end tasks (synthesis, STA, power, floorplanning), collaborate across performance/middle-end/back-end teams, and contribute to pre- and post-silicon verification and debugging.

Lead a team in verifying complex IC designs, develop verification strategies, and ensure high-quality silicon through advanced methodologies and collaboration.

Lead end-to-end physical implementation of high-speed PCIe controller and PHY blocks from netlist to GDSII. Perform floorplanning, placement, CTS, routing, STA, timing closure across PVT corners, power integrity (IR/EM) analysis, DRC/LVS/ERC signoff with Calibre, and tapeout support. Collaborate with RTL, synthesis, DFT, and verification teams and contribute to PD methodology and automation scripting.