Implement ISP algorithms in hardware using Verilog, SystemVerilog, or SystemC; define architectures based on product and performance requirements; estimate gate count and power; verify ISP and digital-system logic; optimize designs for efficiency; and collaborate with ISP algorithm teams.
Responsibilities:
- Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
- Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
- Verify Logic at ISP level and Digital System level
- Optimize Design for less gate count and low power consumption
- Drive ISP Design activities in close collaboration with ISP Algorithm Team
Requirements:
- Minimum MSEE, or BSEE, or equivalent, plus 3+ years of Digital Design and verification related experience
- Experience / knowledge in CMOS Image Sensor and image signal processing (ISP)
- Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.
- Strong debugging and problem-solving skills
- Good communication and interpersonal skills
- Result oriented and adaptable to changes
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What you need to know about the Singapore Tech Scene
The digital revolution has driven a constant demand for tech professionals across industries like software development, data analytics and cybersecurity. In Singapore, one of the largest cities in Southeast Asia, the demand for tech talent is so high that the government continues to invest millions into programs designed to develop a talent pipeline directly from universities while also scaling efforts in pre-employment training and mid-career upskilling to expand and elevate its workforce.
