Jobs at OMNIVISION

Develop and deploy advanced design verification methodologies for increasingly complex hardware designs. Apply UVM, C/C++ co-simulation, system emulation, mixed-mode simulation, and formal verification to achieve zero-defect results. Collaborate with verification teams, communicate effectively, and uphold high quality standards. Candidates may be considered for Senior or Staff responsibilities based on experience. Video processing, video analytics, and strong general programming skills are advantageous.

Lead signal and power integrity signoff for chip, package, and PCB designs. Model high-speed I/O, power delivery networks, and EMC issues; define electrical specifications; support customers with hardware signoff and debugging. Collaborate globally with design, test, physical implementation, and applications teams. Use electromagnetic, transmission-line, and microwave theory, simulation tools, laboratory equipment, and scripting for data processing.

Implement ISP algorithms in hardware using Verilog, SystemVerilog, or SystemC; define architectures based on product and performance requirements; estimate gate count and power; verify ISP and digital-system logic; optimize designs for efficiency; and collaborate with ISP algorithm teams.

Design and develop NPU microarchitectures from system requirements, including RTL coding in Verilog/SystemVerilog, performance modeling, and PPA optimization. Collaborate with verification, software, compiler, and toolchain teams; resolve lint, timing, CDC, and integration issues; support testing and debugging; and produce design documentation. The role requires completed NPU design experience, substantial digital and SoC design expertise, and may involve leading a small engineering team.

Implements ISP algorithms in hardware using Verilog, SystemVerilog, or SystemC. Verifies logic at ISP and digital-system levels, optimizes designs for gate count and power consumption, and collaborates with ISP algorithm teams. Requires an engineering degree, RTL and verification knowledge, C/C++ programming experience, strong debugging skills, communication abilities, adaptability, and results orientation. SystemC with high-level synthesis experience and CMOS image sensor knowledge are preferred.

Develop and enhance toolchain features for neural processing unit architectures, enabling customers and partners to optimize and port AI models. Responsibilities include compiler development, code generation, program analysis, pipeline optimization, model-layer modification, automation, debugging, collaboration with inference and application engineering teams, and customer support.

Develop and enhance image and video processing algorithms for camera applications, improving functionality, quality, and performance. Support algorithm implementation, testing, and verification across teams; drive hardware productization; document algorithms; and collaborate with external researchers. The role requires image processing expertise, digital photography and image quality assessment knowledge, C/C++ proficiency, strong communication, teamwork, and the ability to learn. Experience with ISP or CMOS image sensor algorithm deployment and color or image processing techniques is advantageous.

Lead a hardware verification team developing advanced methodologies for complex SoC designs. Oversee test-plan reviews, execution, analysis, and quality objectives using UVM, co-simulation, emulation, mixed-mode simulation, and formal verification. Apply ASIC verification expertise, EDA tools, programming, and system-level verification practices while coordinating team performance and delivery.

Leads ISP RTL hardware design, architecture, verification, power and gate-count optimization using Verilog, SystemVerilog, SystemC, and HLS. Collaborates with algorithm and digital system teams while managing, mentoring, and supervising RTL design engineers. Defines hardware implementations based on product and performance requirements and oversees timely delivery across teams.

Designs and architects digital SoC platforms for video processing, neural processing, and camera analytics. Responsibilities include defining SoC architectures, developing RTL in Verilog/SystemVerilog, measuring power, timing, and area, and supporting comprehensive verification through successful silicon implementation. The role also involves processor-system integration, embedded C and assembly programming, scripting, system modeling, simulation, and cross-functional collaboration.