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Top Tech Jobs & Startup Jobs in Singapore
Semiconductor
The Layout Engineer is responsible for layout design, floor-planning, and quality verification while adhering to guidelines and methodologies. They should have extensive experience and the ability to work independently as well as lead teams.
Top Skills:
Cadence Layout Tools VirtuosoCalibreScript ProgrammingSkill Programming
Semiconductor
The Technical Adoption Manager will advise enterprise customers on leveraging VMware's technology to achieve business success, guiding them through onboarding, adoption, and realization of value in their cloud operating models.
Top Skills:
Aria AutomationAria Operations ManagerAria SuiteCloud ServicesNsxVcfVcloud DirectorVmc/AwsVMwareVsphereVvf
Semiconductor
Develop high-speed custom analog IC designs, verify connectivity, improve methodologies, and complete PCB layouts for storage applications.
Top Skills:
Cadence AllegroCadence Virtuoso Xl
Semiconductor
The Test Development Engineer will create and integrate ATE test programs, perform validations, and support hardware design while managing multiple projects and improving test methodology.
Top Skills:
Advantest Smartest Ps1600AteExa Scale
Semiconductor
The Staff Engineer will develop automation flows for Place and Route and STA for digital IP subsystems, ensuring timing closure and minimal violations in complex designs.
Top Skills:
Cadence Timing ClosureIcc2InnovusPerlPerlPrime TimePtsiPythonStar-RcSynopsys Timing Closure ToolsTcl
Semiconductor
The Layout Engineer is responsible for applying layout guidelines, completing quality layout and verification, and leading projects. Requires strong layout knowledge and experience with CMOS processes and Cadence tools.
Top Skills:
Cadence Layout Tools VirtuosoCalibre Verification ToolsScript ProgrammingSkill Programming
Semiconductor
As a Layout Engineer, you'll design layout for memory and I/O circuits, ensuring compliance with guidelines and overseeing quality verification processes.
Top Skills:
Cadence LayoutCadence Schematic CaptureCalibreHerculesScript ProgrammingSkill ProgrammingVirtuoso
Semiconductor
The Senior Engineer will develop automation flows for Place and Route, ensuring timing closure, and interact with cross-functional teams on design constraints and timing violations.
Top Skills:
Cadence Timing ToolsIcc2InnovusPerlPnr ToolsPythonSynopsys Timing Tools
Semiconductor
The Senior Design Engineer will develop automation flows for Place and Route and Static Timing Analysis, ensuring timing closure for complex digital systems.
Top Skills:
Fusion CompilerIcc2InnovusPerlPrimetimePythonTcl
Semiconductor
The Senior Engineer will develop automation flows for Place and Route and Static Timing Analysis, collaborating across teams to achieve timing closure and DRC/LVS compliance for advanced digital IP subsystems.
Top Skills:
Icc2InnovusPerlPrime TimePtsiPythonStar-RcSynopsys Timing Closure ToolsTcl
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