Top Tech Jobs & Startup Jobs in Singapore

Lead development, optimization, qualification, and manufacturing transfer of III-V epitaxial growth and wafer fabrication processes for semiconductor devices. Responsibilities include MOCVD process development, yield and quality improvement, NPI support, troubleshooting, technology transfer, data analytics, AI/ML, statistical process control, advanced characterization, and failure analysis.

Design and implement large-scale integrated circuits using commercial and in-house EDA tools across advanced 7nm to 2nm process technologies. Manage complete RTL-to-GDS or gates-to-GDS implementation flows, including placement, clock tree synthesis, routing, physical and formal verification, and timing analysis. Apply UNIX/Linux and Tcl or Bash scripting, with front-end design and synthesis knowledge beneficial.

Develop and verify DFT architectures for hierarchical SoC and ASIC designs. Responsibilities include scan and test point insertion, test compression, SSN topology validation, boundary scan integration, ATPG pattern generation, fault coverage analysis, gate-level verification, and STIL/WGL pattern validation. Collaborate with physical design and ATE teams, support silicon bring-up, and debug production test failures using Siemens Tessent and scripting languages.

Lead physical design implementation for large, high-performance ASICs using advanced 5nm, 3nm, and 2nm processes. Apply commercial and internal EDA tools, resolve timing violations with RTL and physical design teams, support customers, manage technical relationships, and develop innovative design flows for computing and networking products.

Develop and verify DFT architectures for hierarchical SoC and ASIC designs, including scan insertion, test compression, boundary scan, ATPG, and fault coverage analysis. Perform gate-level verification, validate SSN topologies, balance scan chains, and resolve timing challenges. Collaborate with physical design and ATE teams on tester-compatible STIL/WGL patterns, support silicon bring-up, and debug production test failures.

Design and implement large-scale integrated circuits using commercial and in-house EDA tools across advanced 7nm to 2nm process technologies. Manage complete RTL-to-GDS or gates-to-GDS flows, including placement, clock tree synthesis, routing, physical and formal verification, and timing analysis. Apply UNIX/Linux and scripting skills in Tcl, Bash, and Python. A degree in electrical, electronics, or computer engineering and at least five years of relevant experience are required.

Develop and verify DFT architectures for hierarchical SoC and ASIC designs, including scan insertion, test compression, boundary scan, ATPG, and DFT verification. Validate SSN topologies, scan balancing, clock-domain crossings, and tester patterns. Collaborate with physical design and ATE teams on timing, production readiness, silicon bring-up, diagnostics, and failure analysis.

Design and implement large-scale ASICs from RTL or gates through GDS using commercial and in-house EDA tools. Responsibilities include synthesis, placement, clock tree synthesis, routing, physical and formal verification, and timing analysis for advanced-node 7nm to 2nm integrated circuits. GPU, CPU, or DSP architecture knowledge and UNIX/Linux scripting experience are advantageous.

Develop and verify DFT architectures for hierarchical SoC and ASIC designs, including scan insertion, test points, compression, boundary scan, ATPG, and gate-level verification. Analyze fault coverage, validate SSN topology and scan chains, generate tester-compatible STIL/WGL patterns, and collaborate with physical design and ATE teams. Support silicon bring-up, production test debugging, diagnostics, and failure analysis.

Design and verify DFT architectures for hierarchical SoC and ASIC designs. Responsibilities include scan insertion, test point insertion, compression, SSN validation, boundary scan integration, ATPG generation, fault coverage analysis, gate-level verification, and STIL/WGL pattern validation. Collaborate with physical design and ATE teams, support timing resolution, silicon bring-up, production test debugging, diagnostics, and failure analysis.