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Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G. Responsibilities include package layout and routing, high-speed SerDes and RF structures, impedance matching, signal and power integrity, thermal management, manufacturability, reliability, and coordinating multiple projects with global teams and external vendors.

Design and verify CMOS I/O and analog/mixed-signal circuits, including references, op-amps, comparators, and power-on-reset circuits. Run AC/DC, signal integrity, jitter, power, reliability, and EMIR analyses. Collaborate with layout teams, create Verilog, Liberty, and IBIS models, document designs, and support chip integration and silicon bring-up. The role requires advanced-node CMOS expertise, knowledge of I/O protocols, and proficiency with Cadence Virtuoso and SPICE/Spectre simulation.

Leads an electrical engineering team developing and testing IO and analog mixed-signal IP. Oversees project delivery, technical troubleshooting, quality assurance, verification efficiency, resource allocation, documentation, and collaboration with global cross-functional teams and customers. Provides expertise in ESD, latch-up, transmitter and receiver architectures, analog circuits, and digital implementation flows while mentoring engineers and supporting diverse Broadcom business applications.

The Epitaxy Fab Assistant performs functions related to Epi wafers, operating reactors and supporting tools, and calibrating process equipment in a fab environment.

Lead product definition, design, test, and characterization for isolation products. Drive R&D programs with cross-functional teams, perform yield analysis and failure investigations, establish test setups and ATE testing, and support validation and manufacturing handoff to achieve quality, yield, and reliability targets.

Lead development, optimization, and transfer of wafer fabrication processes (thin-film deposition, wafer thinning, thermal processes, implantation) to meet yield, quality, cost, and reliability targets. Drive yield improvement, defect reduction, DOE/SPC experiments, root-cause analysis, and process transfer to high-volume manufacturing. Collaborate cross-functionally, mentor junior staff, and manage supplier process and material improvements.

Lead development, optimization, and transfer of wafer fab processes (thin film, wafer thinning, thermal). Drive yield improvement and defect reduction using SPC/DOE/FMEA, perform root-cause analysis and corrective actions, define control plans and OCAP, support NPI and high-volume transfer, collaborate cross-functionally, mentor junior staff, and interface with suppliers.

Develop, qualify, and sustain photolithography and etch processes for III-V wafer fabrication. Establish process windows, qualify materials and equipment, perform DOE and statistical analysis, support manufacturing and yield improvement, troubleshoot process excursions, and maintain process control documentation (WI, PFMEA, OCAP, recipes, ECO).

Design and verify high-speed analog/mixed-signal IPs (SerDes, HBM, UCIe, PLL) for advanced CMOS nodes. Develop schematics, perform pre/post-layout verification and simulations (Cadence Virtuoso/Spectre), optimize low-jitter/low-power circuits, support layout reviews, assist IP integration into SoCs, and aid silicon bring-up, debug, and characterization.

The role involves designing custom packages for advanced silicon nodes, managing IC packaging activities, developing new materials, and ensuring quality through collaboration across teams.