Top Tech Jobs & Startup Jobs in Singapore

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G. Responsibilities include package layout and routing, high-speed SerDes and RF structures, impedance matching, signal and power integrity, thermal management, manufacturability, reliability, and coordinating multiple projects with global teams and external vendors.

Designs and verifies digital IC layouts for memory, I/O, and standard-cell libraries using Cadence and physical verification tools. Responsibilities include floor planning, hierarchical layout, chip integration, applying process rules, meeting schedules, documenting methodologies, and independently delivering quality layouts. The role may lead or train junior engineers and support new technology reviews. Strong memory-layout experience is emphasized, with analog layout, memory compiler, and SKILL programming experience as advantages. Immediate relocation to Singapore is required.

Develop and integrate DFT architectures for hierarchical SoC and ASIC designs, including scan insertion, test compression, boundary scan, and ATPG. Verify DFT implementations through Verilog and gate-level simulation, analyze fault coverage, and resolve timing challenges. Collaborate with physical design and ATE teams to validate tester patterns, support production readiness, and debug silicon bring-up and test failures.

Develops and supports CAD tool flows for advanced semiconductor process nodes. Responsibilities include resolving design and layout issues, maintaining PDK environments, working with EDA vendors and process teams, developing productivity utilities, supporting physical verification and simulation flows, creating QA infrastructure, documenting tools, and training design engineers.

Design and verify CMOS I/O and analog/mixed-signal circuits, including references, op-amps, comparators, and power-on-reset circuits. Run AC/DC, signal integrity, jitter, power, reliability, and EMIR analyses. Collaborate with layout teams, create Verilog, Liberty, and IBIS models, document designs, and support chip integration and silicon bring-up. The role requires advanced-node CMOS expertise, knowledge of I/O protocols, and proficiency with Cadence Virtuoso and SPICE/Spectre simulation.

Leads an electrical engineering team developing and testing IO and analog mixed-signal IP. Oversees project delivery, technical troubleshooting, quality assurance, verification efficiency, resource allocation, documentation, and collaboration with global cross-functional teams and customers. Provides expertise in ESD, latch-up, transmitter and receiver architectures, analog circuits, and digital implementation flows while mentoring engineers and supporting diverse Broadcom business applications.

Lead development, optimization, and transfer of wafer fab processes (thin film, wafer thinning, thermal). Drive yield improvement and defect reduction using SPC/DOE/FMEA, perform root-cause analysis and corrective actions, define control plans and OCAP, support NPI and high-volume transfer, collaborate cross-functionally, mentor junior staff, and interface with suppliers.

Develop, qualify, and sustain photolithography and etch processes for III-V wafer fabrication. Establish process windows, qualify materials and equipment, perform DOE and statistical analysis, support manufacturing and yield improvement, troubleshoot process excursions, and maintain process control documentation (WI, PFMEA, OCAP, recipes, ECO).

Validate mixed-signal ICs for low-power, high-performance data center storage. Plan and execute product validation, design and debug test and measurement setups (hardware, software, systems), analyze results, and provide feedback to improve product design and test methodology.

Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Plan and perform transistor-to-block-level floorplanning, apply design rules and verification (DRC/LVS/ERC/antenna/EM-IR), and collaborate with senior engineers to adopt methodologies and meet project schedules.