Top Tech Jobs & Startup Jobs in Singapore

Lead end-to-end physical implementation of high-speed PCIe controller and PHY blocks from netlist to GDSII. Perform floorplanning, placement, CTS, routing, STA, timing closure across PVT corners, power integrity (IR/EM) analysis, DRC/LVS/ERC signoff with Calibre, and tapeout support. Collaborate with RTL, synthesis, DFT, and verification teams and contribute to PD methodology and automation scripting.

Design and implement Verilog RTL for SoC blocks, integrate IPs, and support synthesis, timing closure, power optimization, and floorplanning. Contribute to design verification and emulation, assist with pre- and post-silicon debugging, and automate design tasks with scripting.

Develop and execute comprehensive, coverage-driven verification environments using SystemVerilog/UVM. Implement testbenches, run RTL simulations/emulation (Palladium/HAPS/Zebu), debug RTL, maintain regression suites, improve coverage metrics, and document verification results.

Manage end-to-end procurement for AI compute: supplier development, RFQ, negotiation, contracts, and delivery for GPU/CPU servers, EDA software, datacenter services; track market trends, control spend, mitigate cross-border and licensing risks, and report on supplier performance.

Build and maintain cycle-approximate and analytical full-chip performance models (tile array, NoC, memory, IO) in C++/SystemC and Python; analyze LLM/CNN workloads and rooflines; model traffic, contention, memory QoS; run architectural sweeps and provide recommendations; collaborate with compiler and design teams; validate models against RTL/emulation/silicon and deliver reporting/dashboards for leadership.

Lead a team in verifying complex IC designs, develop verification strategies, and ensure high-quality silicon through advanced methodologies and collaboration.

Develop and execute test plans for digital design verification, manage regressions and coverage, and collaborate with design teams to ensure design correctness.

Integrate and customize a commercial RISC-V core soft IP, perform RTL (Verilog/SystemVerilog) front-end and control-path modifications, tailor microarchitecture for PPA, support ASIC front-end tasks (synthesis, STA, power, floorplanning), collaborate across performance/middle-end/back-end teams, and contribute to pre- and post-silicon verification and debugging.

Design and implement Verilog RTL for PCIe-related IP blocks, drive verification closure and functional coverage, assist pre- and post-silicon debug, and collaborate with verification and software teams to deliver robust SoC/IP solutions.

Operate and harden Kubernetes-based AI/MaaS production environments; define SLOs, alerting, dashboards, and runbooks; improve rollout safety with canaries and fast rollbacks; drive GPU capacity planning; automate operations with Helm, Argo CD, operators and scripts; and partner to debug incidents from API edge to model workers.