Top Tech Jobs & Startup Jobs in Singapore

Manage end-to-end procurement for AI compute: supplier development, RFQ, negotiation, contracts, and delivery for GPU/CPU servers, EDA software, datacenter services; track market trends, control spend, mitigate cross-border and licensing risks, and report on supplier performance.

Develop and execute comprehensive, coverage-driven verification environments using SystemVerilog/UVM. Implement testbenches, run RTL simulations/emulation (Palladium/HAPS/Zebu), debug RTL, maintain regression suites, improve coverage metrics, and document verification results.

Own architecture of a 3D-DRAM memory subsystem for an NPU: design controller microarchitecture, address/bank mapping, QoS, refresh/ECC/RAS and thermal-aware throttling; specify PHY/vendor interfaces; build cycle-approximate performance models; define verification and co-verification plans; and lead vendor and cross-team integration through silicon bring-up.

Design and implement Verilog RTL for SoC blocks, integrate IPs, and support synthesis, timing closure, power optimization, and floorplanning. Contribute to design verification and emulation, assist with pre- and post-silicon debugging, and automate design tasks with scripting.

Design and implement Verilog RTL for PCIe-related IP blocks, drive verification closure and functional coverage, assist pre- and post-silicon debug, and collaborate with verification and software teams to deliver robust SoC/IP solutions.

Integrate and customize a commercial RISC-V core soft IP, perform RTL (Verilog/SystemVerilog) front-end and control-path modifications, tailor microarchitecture for PPA, support ASIC front-end tasks (synthesis, STA, power, floorplanning), collaborate across performance/middle-end/back-end teams, and contribute to pre- and post-silicon verification and debugging.

Lead end-to-end physical implementation of high-speed PCIe controller and PHY blocks from netlist to GDSII. Perform floorplanning, placement, CTS, routing, STA, timing closure across PVT corners, power integrity (IR/EM) analysis, DRC/LVS/ERC signoff with Calibre, and tapeout support. Collaborate with RTL, synthesis, DFT, and verification teams and contribute to PD methodology and automation scripting.

Perform RTL synthesis, logic and power/area optimization, static timing analysis and timing closure for AI accelerators. Collaborate with DFT and physical design teams on floorplanning, P&R, and timing/power debugging. Use formal equivalence checking and scripting for automation to deliver optimized ASIC designs for deep learning workloads.

Build and maintain cycle-approximate and analytical full-chip performance models (tile array, NoC, memory, IO) in C++/SystemC and Python; analyze LLM/CNN workloads and rooflines; model traffic, contention, memory QoS; run architectural sweeps and provide recommendations; collaborate with compiler and design teams; validate models against RTL/emulation/silicon and deliver reporting/dashboards for leadership.

Develop Verilog RTL for RISC-V CPU architectures, drive verification closure and functional coverage, assist pre- and post-silicon debugging, and collaborate with verification and software teams to deliver processor IP.