About Bitdeer:
Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.
Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence.
Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia.
About the role:
We are looking for a Senior Physical Design Engineer to execute physical implementation of high-speed PCIe IP and sub-system for AI chip
You will own the full physical design flow from netlist to GDSII, working closely with circuit design, DFT, and verification teams to deliver silicon-proven, high-performance designs on leading-edge process nodes
What you'll do:
- Own end-to-end physical design flow: floorplanning, placement, CTS, routing, STA, physical verification and signoff for PCIe controller and PHY blocks.
- Perform timing closure for high-speed PCIe Gen 4/5/6 interfaces across PVT corners.
- Drive power integrity analysis including IR drop and electromigration (EM) across the power delivery network.
- Achieve physical verification closure including DRC, LVS, and ERC signoff using Calibre tool.
- Work with RTL and synthesis teams to provide feedback on logic restructuring for timing and area improvement.
- Contribute to internal PD methodology, scripts, and flow automation using Perl and Tcl.
- Support tapeout activities including final GDS merge, fill insertion, and signoff checks.
Required qualifications:
- B.S. / M.S. in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of hands-on physical design experience in advanced TSMC process nodes (N6 and below preferred).
- Strong knowledge of PCIe protocol and high-speed interface physical design constraints.
- Strong hands-on experience with CTS for high-speed designs: CTS strategies, skew balancing, useful skew and multi-corner CTS closure.
- Hands-on proficiency with industry-standard PnR and timing signoff tools ( Cadence Innovus / Synopsys Primetime / Tweaker ).
- Experience in resolving chip level DRC / LVS / EMIR issues for advance nodes.
- Experience in multi-die packaging (WoW, 2.5D / 3D), Thermal / IR / EM signoff, signal integrity, or DFT-aware physical design is plus.
- Proficiency using Python, Perl, Tcl, Make scripting is plus.
- Tape out experience required.
What you will experience working with us:
- A culture that values authenticity and diversity of thoughts and backgrounds;
- An inclusive and respectable environment with open workspaces and exciting start-up spirit;
- Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
- Ability to contribute directly and make an impact on the future of the digital asset industry;
- Involvement in new projects, developing processes/systems;
- Personal accountability, autonomy, fast growth, and learning opportunities;
- Attractive welfare benefits and developmental opportunities such as training and mentoring.
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Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.
Bitdeer Group Singapore, Singapore, SGP Office
Singapore, Singapore
