Jobs at Bitdeer Group

Design and implement scalable Kubernetes control plane architectures (Cluster API, Operators, CRDs), optimize etcd, ensure secure multi-tenant API isolation, enable zero-downtime upgrades and multi-cluster federation, integrate with GPU orchestration, lead design reviews, mentor engineers, and drive platform reliability.

Design, deploy, and maintain CSI drivers and GPUDirect Storage integrations for high-performance file systems; implement NVMe caching and optimize IOPS/throughput/latency across containerized storage. Collaborate on RDMA/InfiniBand tuning, define Kubernetes storage policies and multi-tenancy isolation, implement monitoring/alerting, and mentor junior engineers.

Join an 18-month graduate/early-career program to build large-scale AI cloud infrastructure: GPU VMs, bare-metal, managed Kubernetes, distributed training and inference, AI Agent platforms, observability, networking, storage, and automation for global AI workloads.

Design, implement, and operate advanced batch and gang scheduling systems for large-scale AI/HPC clusters. Build admission control, queueing, topology-aware placement, DRA and custom scheduler plugins, and GPU-sharing/multi-tenancy solutions. Integrate scheduling with bare-metal hardware and storage, resolve contention and deadlocks, and mentor engineers to maintain scalable, reliable orchestration stacks.

Design and scale high-cardinality telemetry for AI datacenters: integrate hardware exporters into Kubernetes, build eBPF diagnostics, create alerting/dashboard pipelines, enable multi-tenant billing metrics, define observability standards, and lead architecture reviews and mentoring.

Build and maintain a NetDevOps automation platform: implement device drivers and APIs for multi-vendor equipment, deploy monitoring/observability with Prometheus/Grafana and streaming telemetry, develop IPAM APIs, integrate DCIM/CMDB, and create automated config deployment, change management, and backup/version control workflows.

Design, tune, and maintain GPU hardware and fabric integrations for containerized AI workloads. Optimize host networking (RDMA, SR-IOV, RoCEv2, InfiniBand), implement GPU slicing (MIG, vGPU), build DCGM-based remediation pipelines, profile kernel/driver/runtime (CUDA, NCCL), and collaborate with scheduling/storage teams. Lead investigations, enforce bare-metal provisioning and firmware/OS standards, mentor engineers, and document the AI hardware stack.

The Senior Legal Counsel will provide legal support for capital markets transactions, compliance with SEC regulations, M&A, and corporate governance at Bitdeer.

Lead global treasury front office: FX risk management and hedging, liquidity and cash optimization, bank relationship management, trade/project financing, TMS implementation, governance, and treasury advisory across jurisdictions.

Operate and monitor large-scale datacenter networks for AI workloads, lead incident response, troubleshoot GPU-cluster networking (jitter, NCCL throughput), manage tickets and change control, produce reports, and coordinate with R&D and customers.

Lead end-to-end physical implementation of high-speed PCIe controller and PHY blocks from netlist to GDSII. Perform floorplanning, placement, CTS, routing, STA, timing closure across PVT corners, power integrity (IR/EM) analysis, DRC/LVS/ERC signoff with Calibre, and tapeout support. Collaborate with RTL, synthesis, DFT, and verification teams and contribute to PD methodology and automation scripting.

Design and implement Verilog RTL for SoC blocks, integrate IPs, and support synthesis, timing closure, power optimization, and floorplanning. Contribute to design verification and emulation, assist with pre- and post-silicon debugging, and automate design tasks with scripting.

Develop and execute comprehensive, coverage-driven verification environments using SystemVerilog/UVM. Implement testbenches, run RTL simulations/emulation (Palladium/HAPS/Zebu), debug RTL, maintain regression suites, improve coverage metrics, and document verification results.

Manage end-to-end procurement for AI compute: supplier development, RFQ, negotiation, contracts, and delivery for GPU/CPU servers, EDA software, datacenter services; track market trends, control spend, mitigate cross-border and licensing risks, and report on supplier performance.

Build and maintain cycle-approximate and analytical full-chip performance models (tile array, NoC, memory, IO) in C++/SystemC and Python; analyze LLM/CNN workloads and rooflines; model traffic, contention, memory QoS; run architectural sweeps and provide recommendations; collaborate with compiler and design teams; validate models against RTL/emulation/silicon and deliver reporting/dashboards for leadership.

Lead a team in verifying complex IC designs, develop verification strategies, and ensure high-quality silicon through advanced methodologies and collaboration.

Develop and execute test plans for digital design verification, manage regressions and coverage, and collaborate with design teams to ensure design correctness.

Integrate and customize a commercial RISC-V core soft IP, perform RTL (Verilog/SystemVerilog) front-end and control-path modifications, tailor microarchitecture for PPA, support ASIC front-end tasks (synthesis, STA, power, floorplanning), collaborate across performance/middle-end/back-end teams, and contribute to pre- and post-silicon verification and debugging.

Design and implement Verilog RTL for PCIe-related IP blocks, drive verification closure and functional coverage, assist pre- and post-silicon debug, and collaborate with verification and software teams to deliver robust SoC/IP solutions.

Operate and harden Kubernetes-based AI/MaaS production environments; define SLOs, alerting, dashboards, and runbooks; improve rollout safety with canaries and fast rollbacks; drive GPU capacity planning; automate operations with Helm, Argo CD, operators and scripts; and partner to debug incidents from API edge to model workers.