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Assist in developing and debugging test programs for silicon products, work with engineers on load boards, analyze test data, and support production ramp.

Perform back-end digital implementation for mixed-signal SoCs: block/chip floorplanning, place-and-route, clock-tree synthesis, power and timing optimization, parasitic generation, STA, LVS/DRC, signal integrity and rail analysis, data prep for analog/RF IP, PnR flow maintenance and feature development.

The Senior Design Engineer will contribute to digital design, block architecture, SoC integration, verification, and documentation in low-power MCU and wireless products.

Lead product engineering from NPI through launch and early manufacturing ramp. Define test strategies, guardbands, and reliability stress patterns. Analyze yield and test data, drive root-cause analysis and corrective actions, monitor production metrics, design burn-in hardware, support JEDEC/AEC qualification, and mentor junior engineers.