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The Senior Physical Design Engineer will manage physical design from RTL to GDSII, ensuring timing and power closure, and collaborate on advanced technology nodes for multi-gigabit transceivers.

Design layout for advanced node CMOS products including floor planning and circuit integration while minimizing parasitic effects and ensuring compliance with EMIR and DRC rules.

Design and verify advanced mixed-signal IC products, focusing on complex circuits like PLLs, ADCs, and regulators, while collaborating across teams.

Design and verify advanced analog mixed-signal circuits for connectivity applications, focusing on high-speed data transmission and CMOS technology.