Top Tech Jobs & Startup Jobs in Singapore

Lead root cause analysis of device failures using advanced tools, collaborate with teams on designs, and monitor wafer reliability performance.

Lead and optimize III-V epitaxial growth processes primarily using MOCVD for semiconductor devices, supporting R&D and production with focus on yield improvement and process quality.

Design and execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced nodes. Manage floorplanning, follow verification rules, collaborate across sites, adopt new methodologies, and lead documentation and project management tasks.

Senior IC layout engineer responsible for high-quality layout and verification for memory, I/O and standard cells at advanced submicron nodes. Tasks include floorplanning, layout implementation, DRC/LVS/ERC/Antenna/EM verification, methodology documentation, mentoring junior engineers, and meeting schedules. Must relocate to Singapore.

Provide hands-on CAD tool flow development and day-to-day support for advanced-process node layout and design issues. Develop and maintain Calibre DRC/LVS decks, CAD PDK environments, EDA simulation flows (Spectre, Hspice), and block-level place-and-route flows. Support QA, testing, releases, user support, documentation, and productivity utilities.

The R&D Test Engineer will develop ATE test programs and hardware, research new testing methodologies, and collaborate with a multi-functional team on product releases.

Validate mixed-signal ICs for low-power, high-performance data center storage. Plan and execute product validation, design and debug test and measurement setups (hardware, software, systems), analyze results, and provide feedback to improve product design and test methodology.

The Epitaxy Fab Assistant operates reactors and testing equipment, performing Epitaxy functions in wafer growth and testing within a fab environment.

Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Plan and perform transistor-to-block-level floorplanning, apply design rules and verification (DRC/LVS/ERC/antenna/EM-IR), and collaborate with senior engineers to adopt methodologies and meet project schedules.

Design and execute IC layouts for memory, I/O and standard cells using Cadence Virtuoso and verification tools (Calibre, Hercules). Apply process rules for submicron nodes, perform floor-planning, hierarchy layout, physical verification (LVS/DRC/ERC/antenna/EM), integrate chips, document methodology, and deliver quality layouts on schedule while collaborating with the library team.