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Reposted 12 Days AgoSaved
Remote
Yishun, SGP
Senior level
Senior level
Semiconductor
The R&D Engineer will design analog layouts using CADENCE tools, verify layout compliance, and manage project reviews related to analog IC design.
Top Skills: Cadence VirtuosoMentor Graphics Calibre
Reposted 14 Days AgoSaved
Yishun, SGP
Junior
Junior
Semiconductor
Responsible for layout design, floor-planning, and verification processes. Requires strong knowledge of layout guidelines and tools, with ability to work independently.
Top Skills: Cadence Layout Tools VirtuosoCalibre Verification Tools
Reposted 14 Days AgoSaved
Yishun, SGP
Junior
Junior
Semiconductor
The Layout Engineer will manage layout designs, apply guidelines, verify layouts, and collaborate within a team, ensuring quality and efficiency in the layout process.
Top Skills: Cadence Layout Tools VirtuosoCalibre Verification ToolsScript ProgrammingSkill Programming
Reposted 14 Days AgoSaved
Yishun, SGP
Junior
Junior
Semiconductor
This role involves creating quality layouts, following guidelines for layouts and physical verifications, and working independently on projects.
Top Skills: Cadence Layout Tools VirtuosoCalibre Verification ToolsScript ProgrammingSkill Programming
Reposted 14 Days AgoSaved
Yishun, SGP
Junior
Junior
Semiconductor
Layout Engineer responsible for circuit design in the Library Group, focusing on layout guidelines, scheduling, quality verification, and team collaboration.
Top Skills: Cadence LayoutCadence Schematic CaptureCalibreHerculesSkill ProgrammingVirtuoso
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Reposted 15 Days AgoSaved
Remote
Yishun, SGP
Mid level
Mid level
Semiconductor
The Design Engineer will develop automation flows for Place and Route/STA, collaborate with teams to ensure timing closure, and utilize various tools for analysis and reporting.
Top Skills: Fusion CompilerIcc2InnovusPerlPrime TimePtsiPythonStar-RcSynthesisTcl
Reposted 15 Days AgoSaved
Remote
Yishun, SGP
Mid level
Mid level
Semiconductor
The role involves automating the Place and Route and Static Timing Analysis for digital IP subsystems, facilitating timing closure and DRC/LVS processes.
Top Skills: Fusion CompilerIcc2InnovusPerlPrime TimePtsiPythonStar-RcSynthesisTcl
Reposted 19 Days AgoSaved
In-Office
17 Locations
Senior level
Senior level
Semiconductor
The Technical Adoption Manager will consult customers on VMware solutions, ensure satisfaction, and expand adoption of Application Networking & Security solutions by managing relationships and guiding project leadership.
Top Skills: Application Performance & SecurityBgpCloud InfrastructureFirewallsIds/IpsLoad Balancing TechnologiesNetwork VirtualizationNetworkingOspfVlansVmware Products
Reposted 22 Days AgoSaved
Yishun, SGP
Senior level
Senior level
Semiconductor
The Sales Operations Analyst will optimize processes, analyze data, implement improvements, and support management with insights in semiconductor operations.
Top Skills: Bi ToolsExcelSQL
Reposted 24 Days AgoSaved
Yishun, SGP
Senior level
Senior level
Semiconductor
Join Broadcom's team as a Principal/Senior Analog/RF IC Engineer to develop Analog/Mixed Signal circuits and work with advanced CMOS technology.
Top Skills: AdcsAnalog And Mixed Signal Ip DesignAnalog Ic DesignCmosComparatorsDacsHigh Speed AmplifiersNoise AnalysisPower OptimizationRf Ic DesignSimulation TechniquesSwitched Mode Power Supplies
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