Top Tech Jobs & Startup Jobs in Singapore

Analog Layout Intern supporting analog and mixed-signal integrated circuit layout for high-speed connectivity and broadband applications. Responsibilities include learning device matching, symmetry, floor planning, routing, parasitic awareness, DRC/LVS verification, layout reviews, documentation, collaboration, and potential scripting automation under experienced engineer guidance.

Lead the Test Solutions Engineering team in APAC, focusing on ATE-based test development, new product introduction, and cross-functional collaboration.

Owns end-to-end capacity planning across Marvell’s global OSAT subcontractor network. Develops near- and long-range capacity plans, maintains Kinaxis capacity models, manages constraints and bottlenecks, oversees supplier capacity governance and capital expenditure tracking, and runs scenario planning. Translates planning outputs into operational execution, supports customer fulfillment, builds executive dashboards, and coordinates cross-functional resolution of production issues. Requires semiconductor backend and direct OSAT subcontractor experience, plus S&OP or demand-supply balancing exposure.

Manage global subcontractor bump, sort, assembly, and test capacity to fulfill customer orders on time and cost-effectively. Coordinate production issues, monitor WIP and inventory in Oracle, provide management reporting, collaborate with engineering, quality, and test teams, and support cross-functional projects and system enhancements.

Leads semiconductor product engineering for server and network processors, including digital and analog performance debugging, yield and test optimization, manufacturing specification development, production test flow improvements, customer escalation support, and new product, package, and fab qualification. Collaborates with design, test, hardware, firmware, DFT, DFM, process, and quality teams to improve yield, quality, test time, and defect metrics.

Lead semiconductor ATE test solution development for characterization, production, and wafer sort. Design high-speed test hardware, create test plans, convert simulation patterns to ATE formats, optimize test flows and yields, and release production test programs. Collaborate with design and DFx teams on testability, methodology, and product specifications using Advantest 93K or Teradyne platforms.

Coordinate production issues affecting customer order fulfillment, collaborate with global engineering, test, quality, and other teams, support cross-functional projects, provide management status reports, and maintain subcontractor WIP and inventory reporting in Oracle.

Develops automated test equipment solutions for custom semiconductor products from early design through high-volume manufacturing. Responsibilities include creating test plans, validating yield and reliability, developing screening methods, characterizing silicon variation, performing root-cause analysis, optimizing test margins and efficiency, and collaborating with design, DFT, operations, reliability teams, and customers.

Owns ATE production test solutions for custom semiconductor products from early design through high-volume manufacturing. Responsibilities include test architecture, bring-up, test planning, characterization, yield and performance analysis, fault isolation, root-cause analysis, test margin development, and cross-functional collaboration with design, DFT, operations, reliability teams, and customers.

Lead NPI silicon bring-up and product engineering for networking/switch/processor lines. Drive cross-functional yield analysis, statistical data analysis, test development/debug, root-cause resolution, and implement improvements to meet mass-production release goals.