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Lead development of ATE test solutions and hardware on Advantest/Teradyne platforms; create test plans; convert design patterns to ATE; collaborate with DFx and design teams; optimize test flows to improve yields and reduce test time; release production test programs and support wafer sort and characterization.

Lead the design of sophisticated CMOS transceiver products, overseeing team performance and ensuring successful transitions from concept to production.

The Principal Hardware Design Engineer will lead system architecture design and modeling for high-speed hardware, ensuring alignment with SI and PI requirements while influencing design standards and practices.

Lead high-speed and high-performance SerDes development in advanced technology nodes. Design IPs including SerDes DDR, and support IP characterization and debugging.

Lead the design and development of high-speed validation boards, ensuring performance through collaboration with multiple teams. Perform system-level validation and optimize channel performance.

As a Senior Staff Engineer, you will develop ATE test solutions, design high-speed testing hardware, create test plans, and collaborate with cross-functional teams to ensure product quality and optimize testing processes.

The Senior Staff Engineer will lead NPI phases, analyze performance and yield, collaborate across teams, and enhance product testing processes.

Lead full lifecycle execution for custom silicon programs, driving cross-functional teams to ensure schedule, quality, and cost, while managing risks and relationships with stakeholders.

Lead end-to-end supply chain planning and execution for multiple semiconductor NPI programs from prototype through high-volume manufacturing. Ensure BOM/item setup, WIP tracking, test floor and capacity planning, supplier coordination (foundries, OSATs, test houses), ERP/dashboard-driven execution, and cross-functional alignment to meet launch and ramp milestones while driving process improvements and reporting to senior leadership.

Responsible for the design and verification of circuits for high-speed broadband ICs, including developing DV plans and creating test cases.