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In-Office
Singapore, SGP
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Senior level
Senior level
Hardware • Internet of Things • Software • Wearables • Semiconductor
The Senior Embedded Graphics Software Engineer develops and maintains GPU software stacks, collaborates on graphics APIs, and supports pre- and post-silicon testing.
Top Skills: Arm ArchitectureAssembly LanguageCConfluenceDbiDpiFreertosGitGpuJIRAMvpi DsiOpengl EsPythonZephyr
7 Days AgoSaved
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In-Office
Singapore, SGP
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Expert/Leader
Expert/Leader
Hardware • Internet of Things • Software • Wearables • Semiconductor
Design and implement low-power DFT architecture for ultra-low-power SoCs: scan insertion, boundary scan, MBIST and ATPG; generate and optimize structural test vectors; run pre/post-layout simulations; collaborate with designers and test engineers to resolve timing, power, and logical issues and bring up tests on silicon.
Top Skills: Tcl,Rtl,Atpg,Mbist,Dft,Scan Insertion,Boundary Scan,Scan Compression,Stuck-At,At-Speed,Path-Delay,Standard Eda Tools,Pre/Post-Layout Simulation,Sta,Gls
7 Days AgoSaved
Easy Apply
In-Office
Singapore, SGP
Easy Apply
Senior level
Senior level
Hardware • Internet of Things • Software • Wearables • Semiconductor
Lead and own design verification for digital and mixed-signal SoCs. Develop test plans, build SystemVerilog/UVM reusable testbenches, write C-based test packages, run full-chip/module verification, implement CPF/UPF power-aware flows, automate randomized testing and scoreboarding, debug and perform root-cause analysis, and track coverage and verification metrics while collaborating with design and software teams.
Top Skills: Systemverilog,Uvm,Verilog,C,C++,Python,Perl,Makefile,Arm,Risc-V,Amba Axi,Amba Ahb,Amba Apb,Dma,Cpf,Upf,Uart,Spi,I2C,Audio,Gpu,Display Controller,Usb,Emmc,Cadence Hifi-5,Cadence Hifi-3,Soc,3Rd-Party Ip/Vip,Low-Power Design
7 Days AgoSaved
Easy Apply
In-Office
Singapore, SGP
Easy Apply
Senior level
Senior level
Hardware • Internet of Things • Software • Wearables • Semiconductor
Lead RTL design and pre-tapeout quality for SoC/IP modules: develop micro-architecture, implement RTL in Verilog, integrate 3rd-party IPs, collaborate on verification/FPGA/physical closure, run LINT/CDC/RDC checks, and assist silicon bring-up.
Top Skills: Verilog,Rtl,Soc,Ip Integration,Fpga,Dft,Lint,Cdc,Rdc,Physical Design,Timing Constraints,Silicon Bring-Up,Micro-Architecture
7 Days AgoSaved
Easy Apply
In-Office
Singapore, SGP
Easy Apply
Senior level
Senior level
Hardware • Internet of Things • Software • Wearables • Semiconductor
Lead RTL development and pre-tapeout quality for MCU SOC/IP modules: micro-architecture, Verilog implementation, 3rd-party IP integration, timing/power closure, verification/FPGA collaboration, silicon bring-up, and running/triaging quality tools (LINT, CDC, RDC).
Top Skills: Verilog,Lint,Cdc,Rdc,Fpga,Dft,Physical Design,Timing Constraints,Silicon Bring-Up,Soc,Ip Integration
7 Days AgoSaved
Easy Apply
In-Office
Singapore, SGP
Easy Apply
Senior level
Senior level
Hardware • Internet of Things • Software • Wearables • Semiconductor
Lead end-to-end memory deployments: define memory roadmap, evaluate and simulate memory architectures (SRAM/DRAM/HBM/RRAM/MRAM), lead characterization, work with architects, circuit and process teams, and third-party vendors to ensure energy-efficient, high-yield memory integration.
Top Skills: Sram,Dram,Hbm,Rram,Mram,Memory Compilers,Eda Tools,Circuit Simulation,Layout Design,Semiconductor Manufacturing,Memory Characterization
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