Top Tech Jobs & Startup Jobs in Singapore

Perform block-level and top-level physical design implementation for high-speed transceiver IPs at advanced technology nodes. Responsibilities include floorplanning, placement, CTS, routing, physical verification, timing and power optimization, EM/IR analysis, congestion mitigation, ECOs, IP integration, and tapeout signoff. The role also requires scripting automation and collaboration with RTL, STA, and cross-functional engineering teams.

Design and verify analog and mixed-signal IC layout blocks for high-performance ASICs using advanced CMOS processes. The role requires hardware engineering expertise in VLSI or computer architecture, RTL design and verification skills, scripting, and C/C++ experience. Preferred qualifications include experience with PCIe, DDR, HBM, SerDes, real-world semiconductor design, and Synopsys EDA tools.

Design and verify advanced-node CMOS analog and mixed-signal ICs, including PLLs, ADCs, regulators, amplifiers, transmitters, receivers, and clocking circuits. The role requires transistor-level design, tapeout, lab bring-up, debugging, noise and jitter analysis, and collaboration across global teams. Engineers will use Spectre and MATLAB, contribute to connectivity and optical applications, and apply expertise in RFIC design, PCB development, ESD protection, packaging, and high-speed data transmission.

Design and verify analog and mixed-signal IC layout blocks for advanced CMOS ASICs supporting high-performance computing and networking. The role involves RTL and hardware verification using Verilog, SystemVerilog, UVM, assertions, and functional coverage, along with scripting in Python or Perl and development in C/C++. Familiarity with PCIe, DDR, HBM, SerDes, and Synopsys EDA tools is preferred.

Lead block-level and top-level physical implementation for high-speed transceiver IPs at advanced technology nodes. Responsibilities include floorplanning, placement, CTS, routing, timing and power convergence, EM/IR analysis, congestion mitigation, physical verification, IP integration, ECOs, and tapeout signoff. The role requires collaboration with RTL and STA teams, automation scripting, and hands-on use of industry-standard implementation and signoff tools.

Lead block- and top-level physical implementation for high-speed transceiver IPs: floorplanning, placement, CTS, routing, routing signoff, EM/IR and congestion analysis, timing closure, IP integration, ECO/tapeout support, and automation scripting to optimize area, power, and timing in advanced process nodes.