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This role involves advancing thin film process development for NAND technology through experiments, material characterization, collaboration with teams, and project leadership.

Lead and develop a Procure-to-Pay operations team delivering global P2P support (tail spend, PR/PO processing, supplier onboarding, catalog, receiving, invoice resolution). Own service delivery KPIs, compliance, audit readiness, process documentation, stakeholder escalations, and continuous improvement. Act as P2P SME, drive automation/AI enablement, support system changes and UAT, and partner cross-functionally with Finance, IT, procurement, and suppliers.

The Facilities Engineer is responsible for overseeing UPW and WW systems operations, maintenance, and engineering projects, ensuring compliance and sustainability goals are met.

The role involves developing AI-driven solutions for semiconductor engineering, focusing on GenAI systems, data pipelines, and machine learning models while collaborating with cross-functional teams.

Coordinate with teams to prepare for silicon validation, ensuring product meets expectations through troubleshooting and testing. Provide technical training and support.

Conduct experiments to improve poly-SiGe gap filling in high-aspect-ratio semiconductor structures. Analyze deposition effects on film growth, conformality, voids, seams, pinch-off, and structural integrity using DOE, SEM/TEM cross-sections, and statistical methods. Correlate fill quality with die strength and wafer or block bending, then recommend optimized process windows and qualification plans. Collaborate with engineering teams and subject matter experts throughout the development cycle.

Validate and qualify NAND flash products across pre-silicon and post-silicon stages. Perform simulations with CAD and Verilog, run device characterization and failure analysis, define product configurations, support engineering sample prep, and integrate AI-assisted tools to improve workflows while collaborating cross-functionally to resolve design issues.

The Principal Engineer will lead CMP process development for NAND technologies, optimize processes, collaborate globally, and mentor junior engineers.

Defines and drives chip-package interaction technology strategy and roadmaps for advanced silicon node transitions in next-generation memory products. Leads cross-functional collaboration across silicon, package, assembly, quality, and product development teams to ensure technology readiness, mitigate risks, and execute innovative solutions. The role requires technical leadership and proficiency with AI-based workflows.

Develop and optimize photolithography processes for advanced 3D NAND manufacturing, improving yield, quality, process margins, and cost. Apply artificial intelligence to create photolithography process-development algorithms, evaluate hardware and novel processes, and implement process monitoring and control methods. Collaborate with manufacturing, R&D, suppliers, and global teams to troubleshoot integration issues, adapt technology for future nodes, identify simplification opportunities, and drive technical breakthroughs through patents and publications.