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Responsible for the design and verification of circuits for high-speed broadband ICs, including developing DV plans and creating test cases.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest/Teradyne. Design high-speed ATE hardware, create test plans, convert design patterns to ATE format, collaborate with DFx and Design to improve yield and testability, optimize test flows, and release production test programs.

The Staff Engineer, Analog Layout will design and layout high-performance analog circuits, manage project schedules, and collaborate with teams for custom ICs.

Sustain and operate Marvell's Silicon.da test data analytics platform: monitor and resolve data loading and quality issues, support users via ServiceNow/Slack, coordinate with vendors and foundries, maintain documentation, and drive issue closure and operational readiness.

The Analog Layout Engineer will design and verify high-speed analog circuits using CAD tools, collaborating with global teams to ensure project specifications are met.

As a Senior Analog Layout Engineer, you'll collaborate globally, running simulations and verifications using Cadence Virtuoso while owning the development lifecycle of analog circuit designs.

Lead development and support of advanced physical verification (PV) flows and add-on tools. Develop, deploy, and maintain dual Calibre/ICV signoff flows, onboard third-party IP, integrate PV into the CAD platform, mentor engineers, interface with EDA vendors, and support advanced process nodes and 3DIC/PMIC technologies to ensure timely, high-quality PV signoff.

Work with design, test, DFT/DFM and firmware teams to debug and characterize digital/analog circuits, analyze volume data and lab tests to resolve yield and test issues, define manufacturing/test specs, optimize test flows and time, support RMA/customer escalations, and lead new product and package/fab qualification before volume production.