Design and verify digital RTL for wireless connectivity SoCs and IPs using VHDL or Verilog. Develop low-power, FPGA-friendly, DFT-compliant designs supporting clock domains, functional modes, and SoC integration. Perform simulation, FPGA prototyping, synthesis, and logic equivalence checks, debug design issues, and collaborate with RTL-to-netlist and backend teams throughout the IC lifecycle.

Manage quote approvals, debit extensions, pricing quotations, demand forecasting, revenue tracking, sell-through analysis, and opportunity follow-up for a semiconductor business unit. Collaborate with Sales and Business Marketing teams on large opportunities, deal compliance, quarterly business operations, product-line forecasting, and annual corporate planning. Prepare management presentations and provide analytical insights to support revenue performance and strategic decisions.

Lead PCIe Gen5/Gen6 PHY validation from pre-silicon planning through silicon bring-up, board validation, compliance, interoperability, manufacturing, and customer ramp support. Perform advanced electrical characterization, modeling, simulation, link training debug, margining, and system-level failure isolation across PHY, firmware, boards, packages, connectors, retimers, and platforms. Develop validation strategies, analyze high-speed measurements, support compliance labs and production testing, mentor engineers, and provide technical recommendations to leadership.