Lead the Application, Networking and Security sales organization across APJ, driving strategy and performance in the region.

The Analog Physical Design Engineer will develop high-speed custom analog/mixed-signal ICs for data center storage. Responsibilities include layout of circuits, floor planning, verification processes, and PCB design. The role requires collaboration with engineers and involves methodology improvements for efficiency.

The Layout Engineer is responsible for applying layout guidelines, performing floor-planning and layout design, verifying quality layouts, and quickly adapting to new methodologies. The role requires strong expertise in custom and analog layout design, as well as experience with Cadence tools and physical verifications in CMOS processes. Team leadership and project management skills are also beneficial.

The Analog Physical Design Engineer will design high-speed, high-performance analog/mixed-signal integrated circuits. Responsibilities include working with a team to develop layouts, verifying design rules, improving methodology efficiency, and completing PCB layouts for test hardware.

The Test Development Engineer will create and integrate ATE test programs supporting silicon bring-up for NPI, perform validation and characterization across various parameters, and debug test issues. Responsibilities include supporting ATE hardware design, executing projects, and collaborating with teams for test development and product release.

The Staff Design Engineer will work on Place and Route and STA development for digital IP subsystems and semi-custom macros, focusing on automation flow, timing closure, and cross-functional collaboration to ensure effective design outcomes.

The Layout Engineer will handle layout design and verification tasks, following necessary guidelines and rules to ensure quality. The role involves floor-planning and collaboration within the library team, with a focus on both independent work and teamwork. There is a preference for candidates with 3 to 4 years of experience or fresh graduates in Electronics engineering.

Responsible for layout design in the Library Group, focusing on circuit design for memory, I/O, and standard cells. The role requires extensive layout knowledge, implementation of layout guidelines, management of project timelines, and verification using industry standard tools. Leading junior engineers and adapting to new methodologies are also key responsibilities.

The Senior Engineer will be responsible for Place and Route (PNR) and Static Timing Analysis (STA) development for complex digital IP subsystems. Responsibilities include automating netlist to GDS2 flows, defining timing constraints, collaborating with cross-functional teams, and ensuring timing closure with minimal ECOs. Strong scripting and automation skills are crucial for this role.

The Senior Engineer will focus on Place and Route and STA development for complex digital IP subsystems. Responsibilities include automating netlist to GDS2 flows, defining constraints for timing closure, collaborating with cross-functional teams to resolve violations, and ensuring optimal design through automation techniques.

The Senior Design Engineer will focus on Place and Route (PNR) and Static Timing Analysis (STA) for complex digital IP subsystems. Responsibilities include developing automation flows, defining constraints in ICC, interacting with cross-functional teams for timing closure, and utilizing scripting for automation of PNR/STA workflows.