Jobs at Broadcom

Operates semiconductor fabrication equipment to perform wafer processing functions such as alignment, masking, etching, and diffusion. Calibrates equipment, follows standard procedures, troubleshoots process issues, and implements corrective actions under close supervision. The role involves routine assignments, limited judgment, detailed instructions, and sharing information with the team. Typically requires less than one year of related experience.

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G. Responsibilities include package layout and routing, high-speed SerDes and RF structures, impedance matching, signal and power integrity, thermal management, manufacturability, reliability, and coordinating multiple projects with global teams and external vendors.

Design and verify CMOS I/O and analog/mixed-signal circuits, including references, op-amps, comparators, and power-on-reset circuits. Run AC/DC, signal integrity, jitter, power, reliability, and EMIR analyses. Collaborate with layout teams, create Verilog, Liberty, and IBIS models, document designs, and support chip integration and silicon bring-up. The role requires advanced-node CMOS expertise, knowledge of I/O protocols, and proficiency with Cadence Virtuoso and SPICE/Spectre simulation.

Leads an electrical engineering team developing and testing IO and analog mixed-signal IP. Oversees project delivery, technical troubleshooting, quality assurance, verification efficiency, resource allocation, documentation, and collaboration with global cross-functional teams and customers. Provides expertise in ESD, latch-up, transmitter and receiver architectures, analog circuits, and digital implementation flows while mentoring engineers and supporting diverse Broadcom business applications.

Operates semiconductor fabrication equipment to perform wafer alignment, masking, etching, and diffusion processes. Calibrates and runs process equipment, troubleshoots issues, and implements corrective actions to maintain process control. Follows standard procedures under close supervision, completes routine assignments, learns job skills and company policies, and shares information with the team. Typically requires less than one year of related experience.

The Epitaxy Fab Assistant performs functions related to Epi wafers, operating reactors and supporting tools, and calibrating process equipment in a fab environment.

Operate laboratory equipment to perform process measurements, enter measurement data into systems, inspect materials under a microscope, and prepare items and shipping documents. The role also involves packing, email communication, and completing assigned manufacturing support tasks. Basic computer proficiency in Excel, PowerPoint, and Google Sheets, along with English comprehension, is required.

Operates and calibrates epitaxy reactors, supporting fab tools, and wafer testing equipment in a semiconductor manufacturing environment. Performs epitaxy growth and testing functions, follows standard procedures, supports Total Productive Maintenance initiatives, suggests process improvements, escalates equipment issues, and develops basic maintenance and tool changeover skills.

Operates epitaxy reactors, supporting tools, and wafer testers in a semiconductor fabrication environment. Calibrates and operates process equipment using standard procedures, supports Total Productive Maintenance initiatives, suggests improvements, escalates equipment issues, and develops skills in basic maintenance tasks during tool changeovers.

Lead product definition, design, test, and characterization for isolation products. Drive R&D programs with cross-functional teams, perform yield analysis and failure investigations, establish test setups and ATE testing, and support validation and manufacturing handoff to achieve quality, yield, and reliability targets.

Maintain, troubleshoot, and optimize high-volume semiconductor fab equipment (MOCVD, lithography, PECVD, RIE, metrology, etc.) to maximize uptime, implement preventive maintenance, perform root cause analysis, manage spares and vendor support, and ensure cleanroom safety and compliance.

Lead development, optimization, and transfer of wafer fabrication processes (thin-film deposition, wafer thinning, thermal processes, implantation) to meet yield, quality, cost, and reliability targets. Drive yield improvement, defect reduction, DOE/SPC experiments, root-cause analysis, and process transfer to high-volume manufacturing. Collaborate cross-functionally, mentor junior staff, and manage supplier process and material improvements.

Lead development, optimization, and transfer of wafer fab processes (thin film, wafer thinning, thermal). Drive yield improvement and defect reduction using SPC/DOE/FMEA, perform root-cause analysis and corrective actions, define control plans and OCAP, support NPI and high-volume transfer, collaborate cross-functionally, mentor junior staff, and interface with suppliers.

Develop, qualify, and sustain photolithography and etch processes for III-V wafer fabrication. Establish process windows, qualify materials and equipment, perform DOE and statistical analysis, support manufacturing and yield improvement, troubleshoot process excursions, and maintain process control documentation (WI, PFMEA, OCAP, recipes, ECO).

Design and verify high-speed analog/mixed-signal IPs (SerDes, HBM, UCIe, PLL) for advanced CMOS nodes. Develop schematics, perform pre/post-layout verification and simulations (Cadence Virtuoso/Spectre), optimize low-jitter/low-power circuits, support layout reviews, assist IP integration into SoCs, and aid silicon bring-up, debug, and characterization.

The role involves designing custom packages for advanced silicon nodes, managing IC packaging activities, developing new materials, and ensuring quality through collaboration across teams.

Lead root cause analysis of device failures using advanced tools, collaborate with teams on designs, and monitor wafer reliability performance.

Lead and optimize III-V epitaxial growth processes primarily using MOCVD for semiconductor devices, supporting R&D and production with focus on yield improvement and process quality.

Senior IC layout engineer responsible for high-quality layout and verification for memory, I/O and standard cells at advanced submicron nodes. Tasks include floorplanning, layout implementation, DRC/LVS/ERC/Antenna/EM verification, methodology documentation, mentoring junior engineers, and meeting schedules. Must relocate to Singapore.

Provide hands-on CAD tool flow development and day-to-day support for advanced-process node layout and design issues. Develop and maintain Calibre DRC/LVS decks, CAD PDK environments, EDA simulation flows (Spectre, Hspice), and block-level place-and-route flows. Support QA, testing, releases, user support, documentation, and productivity utilities.