The Finance & Payroll Analyst will manage payroll accounting activities, support international payroll processes, prepare monthly payroll instructions, audit payroll results, and assist with financial reporting and compliance. The role requires collaboration with internal teams and third-party vendors to ensure accuracy and compliance in payroll operations.

The Layout Engineer is responsible for applying layout guidelines, performing floor-planning and layout design, verifying quality layouts, and quickly adapting to new methodologies. The role requires strong expertise in custom and analog layout design, as well as experience with Cadence tools and physical verifications in CMOS processes. Team leadership and project management skills are also beneficial.

The Analog Physical Design Engineer will design high-speed, high-performance analog/mixed-signal integrated circuits. Responsibilities include working with a team to develop layouts, verifying design rules, improving methodology efficiency, and completing PCB layouts for test hardware.

The Test Development Engineer is responsible for creating ATE test programs to support First Silicon bring up, performing design validation, utilizing ATE test tools for debugging, and executing multiple projects to achieve targets. This role requires good communication skills and a team-oriented approach, as well as support for ATE hardware design and test time reduction.

The Staff Design Engineer will work on Place and Route and STA development for digital IP subsystems and semi-custom macros, focusing on automation flow, timing closure, and cross-functional collaboration to ensure effective design outcomes.

The Layout Engineer will handle layout design and verification tasks, following necessary guidelines and rules to ensure quality. The role involves floor-planning and collaboration within the library team, with a focus on both independent work and teamwork. There is a preference for candidates with 3 to 4 years of experience or fresh graduates in Electronics engineering.

Responsible for layout design in the Library Group, focusing on circuit design for memory, I/O, and standard cells. The role requires extensive layout knowledge, implementation of layout guidelines, management of project timelines, and verification using industry standard tools. Leading junior engineers and adapting to new methodologies are also key responsibilities.