Jobs at Broadcom

The Epitaxy Process Engineer will develop and optimize III-V epitaxial growth processes, focusing on MOCVD for high-performance semiconductor devices, while collaborating with teams to enhance manufacturing efficiency.

The candidate will provide technical support for isolation products in automotive applications, conduct training for engineers, design hardware for gate drive and sensing, and perform application testing along with competitive analysis.

Lead and optimize III-V epitaxial growth processes primarily using MOCVD for semiconductor devices, supporting R&D and production with focus on yield improvement and process quality.

Support manufacturing equipment in a Wafer Fabrication plant through maintenance and troubleshooting. Collaborate with engineers and vendors for problem resolution.

Provide hands-on CAD tool flow development and day-to-day support for advanced-process node layout and design issues. Develop and maintain Calibre DRC/LVS decks, CAD PDK environments, EDA simulation flows (Spectre, Hspice), and block-level place-and-route flows. Support QA, testing, releases, user support, documentation, and productivity utilities.

The R&D Test Engineer will develop ATE test programs and hardware, research new testing methodologies, and collaborate with a multi-functional team on product releases.

Validate mixed-signal ICs for low-power, high-performance data center storage. Plan and execute product validation, design and debug test and measurement setups (hardware, software, systems), analyze results, and provide feedback to improve product design and test methodology.

The Epitaxy Fab Assistant operates reactors and testing equipment, performing Epitaxy functions in wafer growth and testing within a fab environment.

Performs wafer fabrication tasks in semiconductor production, operating alignment, masking, etch, and diffusion equipment. Calibrates and runs process tools, troubleshoots to maintain process control, and follows standard procedures under close supervision. Routine assignments; typically requires less than one year of related experience.

Performs wafer fabrication tasks including alignment, masking, etch and diffusion. Operates, calibrates and runs process equipment, troubleshoots processes to meet control parameters, follows standard procedures, and works under close supervision. Routine assignments with limited judgment; typically requires less than one year of related experience.

Performs wafer fabrication tasks in a semiconductor fab, operating and calibrating process equipment for alignment, masking, etch and diffusion. Follows standard procedures, troubleshoots process issues, and implements corrective actions under close supervision. Routine, training-focused role delivering defined outputs.

Perform wafer fabrication tasks including alignment, masking, etch, and diffusion. Operate, calibrate, and run process equipment, troubleshoot process issues, follow standard procedures, and work under close supervision to produce semiconductor devices.

Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Plan and perform transistor-to-block-level floorplanning, apply design rules and verification (DRC/LVS/ERC/antenna/EM-IR), and collaborate with senior engineers to adopt methodologies and meet project schedules.

Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Manage floorplanning and transistor-to-block layouts, apply advanced process rules, run physical verification, and collaborate across engineering teams to meet project schedules.

Design and produce high-quality digital and memory layout (standard cells, I/O, memories) using Cadence Virtuoso and Calibre/Hercules verification. Apply process-specific layout rules, floorplan and integrate chips, lead reviews, mentor junior engineers, and meet schedule and verification targets.

Design and execute IC layouts for memory, I/O and standard cells using Cadence Virtuoso and verification tools (Calibre, Hercules). Apply process rules for submicron nodes, perform floor-planning, hierarchy layout, physical verification (LVS/DRC/ERC/antenna/EM), integrate chips, document methodology, and deliver quality layouts on schedule while collaborating with the library team.

Design and implement IC layouts for standard cells, memory and I/O using Cadence tools. Perform floorplanning, hierarchical layout and physical verification (LVS/DRC/ERC/Antenna/EM) with Calibre and Hercules. Deliver high-quality layouts on schedule, adopt new methodologies, lead documentation and technology reviews, and mentor junior engineers.

Design and verify high-quality IC layouts for standard cells, memory, and I/O using Cadence Virtuoso and Calibre/Hercules. Apply advanced process rules, floorplanning, hierarchical layout, and physical verification (LVS/DRC/ERC/antenna/emigration). Lead junior engineers, document layout methodology, and meet project timelines independently.

Design and verify high-quality digital and memory layout (standard cell, I/O) using Cadence tools and Calibre/Hercules; perform floorplanning, hierarchy layout, integration, and documentation; lead junior engineers and ensure schedules and process-rule compliance.

Design and verify digital and memory layout for advanced submicron CMOS processes. Apply layout rules, floorplan, complete LVS/DRC/ERC and EM checks, lead junior engineers, and document layout methodology to meet schedule and quality targets.