The Director of Customer Experience manages a team to enhance customer engagement and satisfaction, develop strategic service offerings, and maintain strong relationships with senior executives.

The ASIC Physical Design Engineer role requires implementing physical designs of large ASICs and proficiency with various EDA tools and scripting languages.

The ASIC Physical Design Engineer will implement physical designs of large ASICs, utilizing EDA tools and scripting in UNIX/Linux environments, with a focus on performance and configuration of GPUs, CPUs, and DSP architectures.

Support and develop Analog/Mixed Signal tool flows, collaborate with EDA vendors, and maintain tools for design/layout issues.

The CAD Engineer will support and enhance Analog/Mixed Signal tool flows, develop automation software, and collaborate with EDA vendors and technology teams.

The CAD Engineer will develop and validate physical verification decks, support automation, and collaborate on advanced node capability with EDA and foundry teams.

Lead Application Engineering for vSphere Kubernetes Service in the APJ region, defining implementation strategies, engaging customers, and mentoring a technical team for enterprise adoption.

The Application Engineer will drive the success of Broadcom’s VMware Cloud Foundation Advanced Services by collaborating with customers and engineering teams to develop solutions, conduct demos, and support sales efforts.

The role involves guiding enterprise customers in adopting VMware's vSphere Kubernetes Service, focusing on design, validation, and deployment of solutions while collaborating with sales and product management.

Join Broadcom as a Principal/Senior Analog/RF IC Engineer. Responsibilities include designing Analog/Mixed Signal circuits in CMOS technology and working on RF Power Amplifier systems with a strong emphasis on collaboration and expertise sharing.

The Financial Analyst will perform financial planning and analysis, support reporting cycles, provide insights for decision-making, and collaborate with teams to align goals.

The R&D Engineer will design analog layouts using CADENCE tools, verify layout compliance, and manage project reviews related to analog IC design.

Responsible for layout design, floor-planning, and verification processes. Requires strong knowledge of layout guidelines and tools, with ability to work independently.

The Layout Engineer will manage layout designs, apply guidelines, verify layouts, and collaborate within a team, ensuring quality and efficiency in the layout process.

This role involves creating quality layouts, following guidelines for layouts and physical verifications, and working independently on projects.

Layout Engineer responsible for circuit design in the Library Group, focusing on layout guidelines, scheduling, quality verification, and team collaboration.

Responsible for layout design and verification for memory, I/O, and standard cells, managing timelines and ensuring compliance with guidelines. Requires strong knowledge of layout tools and leadership skills.

The Design Engineer will develop automation flows for Place and Route/STA, collaborate with teams to ensure timing closure, and utilize various tools for analysis and reporting.

The role involves automating the Place and Route and Static Timing Analysis for digital IP subsystems, facilitating timing closure and DRC/LVS processes.

The Principal Memory Circuit Design Engineer will develop memory architectures, design memory/circuit blocks, run simulations, and integrate characterization flows.