Teams at Broadcom

Design and verify high-speed analog/mixed-signal IPs (SerDes, HBM, UCIe, PLL) for advanced CMOS nodes. Develop schematics, perform pre/post-layout verification and simulations (Cadence Virtuoso/Spectre), optimize low-jitter/low-power circuits, support layout reviews, assist IP integration into SoCs, and aid silicon bring-up, debug, and characterization.

The role involves designing custom packages for advanced silicon nodes, managing IC packaging activities, developing new materials, and ensuring quality through collaboration across teams.

Drive portfolio growth and new market development (starting AP region). Liaise with R&D/Engineering to support design-in, conduct market research, manage product lifecycle, run channel marketing programs, and develop sales tools and documentation.