Teams at Broadcom

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G. Responsibilities include package layout and routing, high-speed SerDes and RF structures, impedance matching, signal and power integrity, thermal management, manufacturability, reliability, and coordinating multiple projects with global teams and external vendors.

Designs and verifies digital IC layouts for memory, I/O, and standard-cell libraries using Cadence and physical verification tools. Responsibilities include floor planning, hierarchical layout, chip integration, applying process rules, meeting schedules, documenting methodologies, and independently delivering quality layouts. The role may lead or train junior engineers and support new technology reviews. Strong memory-layout experience is emphasized, with analog layout, memory compiler, and SKILL programming experience as advantages. Immediate relocation to Singapore is required.

Develop and integrate DFT architectures for hierarchical SoC and ASIC designs, including scan insertion, test compression, boundary scan, and ATPG. Verify DFT implementations through Verilog and gate-level simulation, analyze fault coverage, and resolve timing challenges. Collaborate with physical design and ATE teams to validate tester patterns, support production readiness, and debug silicon bring-up and test failures.