Broadcom Logo

Broadcom

IC Layout Engineer

Posted 4 Days Ago
Be an Early Applicant
Remote
Hiring Remotely in Yishun, SGP
Mid level
Remote
Hiring Remotely in Yishun, SGP
Mid level
Design and implement IC layouts for standard cells, memory and I/O using Cadence tools. Perform floorplanning, hierarchical layout and physical verification (LVS/DRC/ERC/Antenna/EM) with Calibre and Hercules. Deliver high-quality layouts on schedule, adopt new methodologies, lead documentation and technology reviews, and mentor junior engineers.
The summary above was generated by AI

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

  • Strong layout knowledge with a minimum of 3 to 4 years of experience
  • Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
  • Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm, 2nm, 1.4nm etc
  • Experienced in digital (standard cell, memory, I/O) layout
  • Experienced in analog layout is also a plus

Job Description:

  • Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
  • Schedule time-line & layout floor-planning
  • Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
  • Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

  • Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
  • Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
  • Good experience in Floor-planning, hierarchy layout and chip integration.
  • Knowledge of Script Programming and SKILL Programming would be a plus.
  • Able  to lead  or train a team of junior engineers
  • Good knowledge on memory layout topology.
  • Experience in memory compiler will be a plus.
  • Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
  • Self-reliant, with ability to work independently as well as a team.
  • Good leadership quality on project management.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Broadcom Singapore Office

Singapore

Broadcom Singapore, Singapore, SGP Office

Singapore, Singapore

Broadcom Woodlands, SGP Office

Woodlands, Singapore

Similar Jobs

4 Days Ago
Remote
Yishun, SGP
Junior
Junior
Software • Semiconductor • Manufacturing
Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Plan and perform transistor-to-block-level floorplanning, apply design rules and verification (DRC/LVS/ERC/antenna/EM-IR), and collaborate with senior engineers to adopt methodologies and meet project schedules.
Top Skills: AntennaCadence SkillCadence VirtuosoCalibreDrcEm/IrErcLvsPythonShellTcl
4 Days Ago
Remote
Yishun, SGP
Mid level
Mid level
Software • Semiconductor • Manufacturing
Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Manage floorplanning and transistor-to-block layouts, apply advanced process rules, run physical verification, and collaborate across engineering teams to meet project schedules.
Top Skills: 1.4Nm2Nm3Nm5NmAntennaCadence SkillCadence VirtuosoCalibre (DrcEm/Ir)ErcEsd ProtectionLatch-Up AnalysisLvsPythonShellTcl
4 Days Ago
Remote
Yishun, SGP
Mid level
Mid level
Software • Semiconductor • Manufacturing
Design and verify high-quality IC layouts for standard cells, memory, and I/O using Cadence Virtuoso and Calibre/Hercules. Apply advanced process rules, floorplanning, hierarchical layout, and physical verification (LVS/DRC/ERC/antenna/emigration). Lead junior engineers, document layout methodology, and meet project timelines independently.
Top Skills: 1.4Nm)2Nm3Nm5Nm7NmAntenna ChecksCadence Schematic CaptureCadence VirtuosoCalibreChip IntegrationCmosDrcElectromigrationErcFloorplanningHerculesHierarchical LayoutLvsMemory CompilerSkillSubmicron Processes (16Nm

What you need to know about the Singapore Tech Scene

The digital revolution has driven a constant demand for tech professionals across industries like software development, data analytics and cybersecurity. In Singapore, one of the largest cities in Southeast Asia, the demand for tech talent is so high that the government continues to invest millions into programs designed to develop a talent pipeline directly from universities while also scaling efforts in pre-employment training and mid-career upskilling to expand and elevate its workforce.

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account