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Lumilens

Senior/Staff Process Engineer (Flip Chip)

Reposted 2 Months Ago
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In-Office
Singapore, SGP
Senior level
In-Office
Singapore, SGP
Senior level
Lead development and support of flip chip assembly for silicon photonics, including DOE, material qualification, reliability validation, failure analysis, SPC, and NPI documentation to improve yield and manufacturability.
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Core Responsibilities

  1. Owns the process development and technical support of the Flip Chip process for silicon photonic chip wafers, with OSAT or internal line. Process may include plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.

  2. DOE to characterize process window and margin. Optimize process integration with upstream processes (e.g. bump/FO) to increase yield and manufacturability.

  3. Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including NCP, flux, underfill etc, as applicable.

  4. Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).

  5. Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to FC (e.g. flux void, residue, misalignment, die warpage, reflow anomaly, underfill void etc), and formulate improvement solutions.

  6. Manage incoming material quality control, establish SPC control plans and monitor process variation to ensure long-term process stability.

  7. Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.

 

Key Requirements & Qualifications

  • Education: Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.

  • Experience: 5+ years of hands-on industry experience in flip chip assembly.

    Technical Knowledge:

  • Deep practical understanding of plasma cleaning, flux engineering, pick & place, reflow, underfill, curing and/or TCB/NCP flux-less flow.

  • Comprehensive command of finite element simulation principles regarding warpage, thermal dissipation, and structural mechanical integrity.

  • Solid working expertise with industry validation methodologies including FMEA, SPC controls, and structured 8D problem-solving tools.

  • Software Tools: High proficiency with robust analytical platforms like JMP, Minitab.

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