About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
We are seeking an experienced Analog Layout Design Manager to lead our growing team. This person will be responsible for managing a team of analog layout engineers to deliver high-quality and efficient High Speed integrated circuits (IC) layout design for our cutting-edge products. The successful candidate will have strong leadership skills, deep knowledge of analog layout, and a proven track record in the semiconductor industry.What You Can Expect
Manage a team of analog layout engineers, providing leadership, mentorship, and technical guidance.
Oversee the layout design, and verification in technologies such as CMOS, BiCMOS, etc.
Collaborate with design, TCAD and PD teams to translate circuit designs into physical layouts.
Ensure the team meets project schedules and deliverables, maintaining the highest quality standards.
Conduct layout reviews to ensure design compliance with specifications and adherence to industry best practices.
Coordinate with cross-functional teams for debugging, yield improvement, and issue resolution.
Contribute to layout process and methodology improvements and automation.
Stay updated with the latest technology trends and advancements in the field of analog layout design.
What We're Looking For
Bachelor’s or Master’s degree in Electrical Engineering or related field.
Minimum of 8 years of experience in analog layout design with at least 3 years in a management or team lead role.
Proficiency in industry-standard EDA tools such as Cadence Virtuoso and Calibre.
Deep understanding of semiconductor physics, device fabrication processes, and layout techniques.
Experience in managing layout designs for a variety of analog circuits, including power, high speed, mixed signal, etc.
Exceptional leadership skills with a proven ability to manage and develop a high-performing team.
Strong analytical skills with the ability to solve complex technical problems.
Excellent communication skills with the ability to clearly articulate technical concepts.
Experience with advanced FinFET process nodes.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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