Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
Job Description:
As an Analog Mixed-Signal IC Layout Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include floor planning, creating layout of building blocks and integrating layout for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, antenna rule on top of DRC and LVS. The company seeks a highly motivated and team orientated individual to work with both layout and design engineers across multiple time zone.
Basic Qualifications:
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Bachelor or advanced Diploma degree in EE
Required Experience:
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2+ years of experience developing layout for highspeed analog IC designs in finFET technology
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Experience with layout extraction tools and to analyze layout parasitic to achieve high quality layout for highspeed circuits
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EMIR and antenna DRC rules aware layout practices
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Experience writing SKILL and TCL scripts is highly recommended
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
