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Marvell Technology

Analog IC Design Principal Engineer

Reposted 9 Days Ago
Be an Early Applicant
In-Office
Singapore
Senior level
In-Office
Singapore
Senior level
Lead a team designing CMOS transceiver/SERDES/PLL products, manage analog IP delivery, and oversee architectural investigations and implementations.
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About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

You will be part of a Marvell's central engineering team designing highly sophisticated CMOS transceiver/SERDES/PLL products.

What You Can Expect

  • Lead a team of analog design engineers to interface with layout, verification, and application teams

  • Manage delivery of analog IP to successfully bring designs from concept to production.

  • Architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc.

What We're Looking For

  • Master’s degree and/or PhD Preferred in Electrical Engineering or related fields with 10+ years of experience. A successful candidate should have experience in some of the following designs:

  • PLL, Data Converters, Oscillators and high-speed SerDes design including Receiver and Transmitter design.

  • Experience in Single-ended High Density Parallel Interface for Chip to Chip Communication, DDR5/LPDDR5; GDDR6/LPDDR6 a plus

  • Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must

  • Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.

  • Good understanding of analog layouts in FinFet and its effect on high-speed designs

  • Experienced in system level pre-tape out analog validation

  • Experienced in lab chip bring-up and debugging efforts

  • Strong communication skills

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-VL1

Top Skills

Ade
Cmos
Ddr5
Gddr6
Lpddr5
Lpddr6
Matlab
Spectre
Spice
Virtuoso

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