Teams at Marvell Technology

Lead semiconductor ATE test engineering for characterization, production, and wafer sort using Advantest 93K and/or Teradyne platforms. Develop high-speed test hardware, test plans, test programs, and methodologies; convert simulation patterns to ATE formats; optimize test flows, yields, and test times; and collaborate with design, DFx, and product engineering teams.

Supports hardware engineering activities across semiconductor product lifecycle stages, including requirements planning, supplier engagement, engineering analysis, repair and rebuild cycles, production testing, hardware transfers, cost reduction, quality improvement, and failure analysis. Completes a mentored engineering project focused on hardware deliverables or technical problem-solving and presents the results to engineering stakeholders.

Drive RTL-to-GDS implementation for advanced processors and ASICs, including synthesis, place and route, timing analysis, timing closure, and power, performance, and area optimization. Perform timing and logic ECOs, resolve congestion and implementation issues, and improve physical design methodologies and automation using Tcl, Perl, and Python. Collaborate with RTL, architecture, timing, and CAD teams to deliver high-quality silicon.