Teams at Marvell Technology

Lead development and support of advanced physical verification (PV) flows and add-on tools. Develop, deploy, and maintain dual Calibre/ICV signoff flows, onboard third-party IP, integrate PV into the CAD platform, mentor engineers, interface with EDA vendors, and support advanced process nodes and 3DIC/PMIC technologies to ensure timely, high-quality PV signoff.

The Staff Analog Layout Engineer will design high-performance analog circuits, manage project schedules, collaborate with cross-functional teams, and ensure adherence to design guidelines.

Work with design, test, DFT/DFM and firmware teams to debug and characterize digital/analog circuits, analyze volume data and lab tests to resolve yield and test issues, define manufacturing/test specs, optimize test flows and time, support RMA/customer escalations, and lead new product and package/fab qualification before volume production.