Jobs at Marvell Technology

Lead the Test Solutions Engineering team in APAC, focusing on ATE-based test development, new product introduction, and cross-functional collaboration.

The role involves designing ESD protection schemes, reviewing designs, collaborating with IP designers, and working on advanced process technologies for analog circuits.

Develop and optimize production test hardware and simulation flows for Marvell devices. Use RF and PI simulation tools, script and apply AI automation, collaborate with cross-functional teams, and support ATE integration and bench testing.

Lead NPI silicon bring-up and product engineering for networking/switch/processor lines. Drive cross-functional yield analysis, statistical data analysis, test development/debug, root-cause resolution, and implement improvements to meet mass-production release goals.

The Senior Staff Test Engineer will develop ATE test solutions, create test plans, optimize test flows, and collaborate with cross-functional teams to ensure high-quality silicon semiconductor chips.

Lead APAC learning and organizational development: consult with HR and business leaders, design and deliver learning and OD solutions (virtual and in-person), apply AI/new technologies, measure program effectiveness, drive change management, manage projects and budgets, and build relationships with regional stakeholders and COEs.

The Principal Analog Mixed-Signal IC Design Engineer will design CMOS transceiver products, validate designs, and support integration with digital teams, requiring extensive experience in mixed-signal circuit design and collaboration with engineers.

Lead development of ATE test solutions and hardware on Advantest/Teradyne platforms; create test plans; convert design patterns to ATE; collaborate with DFx and design teams; optimize test flows to improve yields and reduce test time; release production test programs and support wafer sort and characterization.

As a Senior Staff Engineer, you will develop ATE test solutions, design high-speed testing hardware, create test plans, and collaborate with cross-functional teams to ensure product quality and optimize testing processes.

Lead end-to-end supply chain planning and execution for multiple semiconductor NPI programs from prototype through high-volume manufacturing. Ensure BOM/item setup, WIP tracking, test floor and capacity planning, supplier coordination (foundries, OSATs, test houses), ERP/dashboard-driven execution, and cross-functional alignment to meet launch and ramp milestones while driving process improvements and reporting to senior leadership.

Responsible for the design and verification of circuits for high-speed broadband ICs, including developing DV plans and creating test cases.

Lead development of ATE test solutions for characterization, production, and wafer sort on Advantest/Teradyne. Design high-speed ATE hardware, create test plans, convert design patterns to ATE format, collaborate with DFx and Design to improve yield and testability, optimize test flows, and release production test programs.

The Staff Engineer, Analog Layout will design and layout high-performance analog circuits, manage project schedules, and collaborate with teams for custom ICs.

Sustain and operate Marvell's Silicon.da test data analytics platform: monitor and resolve data loading and quality issues, support users via ServiceNow/Slack, coordinate with vendors and foundries, maintain documentation, and drive issue closure and operational readiness.

The Analog Layout Engineer will design and verify high-speed analog circuits using CAD tools, collaborating with global teams to ensure project specifications are met.

As a Senior Analog Layout Engineer, you'll collaborate globally, running simulations and verifications using Cadence Virtuoso while owning the development lifecycle of analog circuit designs.

Lead development and support of advanced physical verification (PV) flows and add-on tools. Develop, deploy, and maintain dual Calibre/ICV signoff flows, onboard third-party IP, integrate PV into the CAD platform, mentor engineers, interface with EDA vendors, and support advanced process nodes and 3DIC/PMIC technologies to ensure timely, high-quality PV signoff.

Work with design, test, DFT/DFM and firmware teams to debug and characterize digital/analog circuits, analyze volume data and lab tests to resolve yield and test issues, define manufacturing/test specs, optimize test flows and time, support RMA/customer escalations, and lead new product and package/fab qualification before volume production.