Jobs at Ambiq

The Senior Embedded Graphics Software Engineer develops and maintains GPU software stacks, collaborates on graphics APIs, and supports pre- and post-silicon testing.

Lead physical implementation of SoCs from netlist to GDS: floorplanning, placement, CTS, routing, verification, and DFM. Drive timing, IR/EM, and signal integrity closure, improve flows and scripts, and collaborate with front-end, DFT, ARC, and package teams using Cadence/Synopsys toolflows for FinFET and multi-patterning processes.

Lead verification of digital and mixed-signal SoC designs. Develop block, subsystem, and chip-level test plans; implement scalable UVM/SystemVerilog testbenches; write C-based SoC tests; apply power-aware CPF/UPF flows; automate randomized testing and scoreboards; debug, perform root-cause analysis, track coverage metrics, and collaborate with design and software teams to deliver chips to spec.

Design, implement, and debug Bluetooth radio firmware for the Apollo Blue family. Develop features, optimize performance and power, write tests, support FAEs, triage validation issues, produce technical documentation, and collaborate cross-functionally to integrate wireless components.

The Senior Embedded Software Engineer will develop, integrate, and verify SDKs for SoC platforms, lead HAL and driver development, and validate embedded systems through collaboration across teams.

Develop, implement, and debug FPGA images for pre-silicon prototyping using Xilinx and Intel toolchains. Collaborate with SoC design, software, verification, and test teams to define timing constraints, support regression test suites, reproduce and triage issues pre- and post-silicon, and perform lab bring-up and instrument-based debugging.

Lead the development and testing of Ambiq's Zephyr software, including driver and software testcase development, maintaining compliance, and solving issues in collaboration with global teams.

Design and implement low-power DFT architecture for ultra-low-power SoCs: scan insertion, boundary scan, MBIST and ATPG; generate and optimize structural test vectors; run pre/post-layout simulations; collaborate with designers and test engineers to resolve timing, power, and logical issues and bring up tests on silicon.