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Internship to develop end-to-end analytics and ML solutions for semiconductor machine and inspection data: data extraction, preprocessing, modeling, drift detection, visualization, and documentation to detect early quality variation signals.

As an Intern Should Cost Analyst, you will analyze data, support procurement objectives, and deliver reporting solutions using various business intelligence tools while collaborating with global teams.

This role involves maintaining and supporting automation applications, collaborating with teams, troubleshooting software issues, and training customers while participating in a 24x7 on-call rotation.

Lead development and validation of next-generation High Bandwidth Memory (HBM) products, optimize manufacturing test coverage and DFT strategy, improve yield and reduce test time through circuit debug and data analysis, mentor team members, and collaborate cross-functionally to meet quality, cost, cycle time, and scale objectives.

Lead and develop a Procure-to-Pay operations team delivering global P2P support (tail spend, PR/PO processing, supplier onboarding, catalog, receiving, invoice resolution). Own service delivery KPIs, compliance, audit readiness, process documentation, stakeholder escalations, and continuous improvement. Act as P2P SME, drive automation/AI enablement, support system changes and UAT, and partner cross-functionally with Finance, IT, procurement, and suppliers.

Lead shift-level process development and operations for TD manufacturing, ensuring process stability, yield protection, and quality. Coordinate priorities with 1st shift, HVM Ops, and cross-functional teams; troubleshoot complex process and equipment issues using data-driven analysis; manage and develop engineers and technicians; drive continuous improvement, capacity planning, and control of chronic tool/process issues.

Lead development and delivery of wafer/cube probe test solutions for HBM devices across NPI to HVM. Drive probe test plans, ATE program development, silicon debug, data-driven yield improvements, probe hardware validation, cost and test-time optimization, and cross-functional alignment. Mentor engineers and standardize probe practices to ensure production readiness and sustained issue closure.

Develop and debug intrinsic and extrinsic reliability test programs for HBM, DRAM, and interface dies (e.g., wafer-level burn-in, pWLRx, ELFR). Perform root-cause analysis, data-driven validation using statistical tools, hardware interface specification and validation, cross-functional collaboration, mentorship, process improvements, and project prioritization to meet quality, cost, and cycle-time KPIs.

Lead electrical engineering and construction for semiconductor fab and cleanroom facilities, overseeing HV/MV/LV power distribution, substations, UPS/generator systems, commissioning, energization, and handover. Ensure compliance with Global Facilities Electrical Standards, coordinate across disciplines, manage change approvals, and drive safety, reliability, and readiness for RFE/RFM.

Perform data exploration, statistical analysis, and visualization on FOUP (wafer carrier) transportation datasets to identify factors affecting transport time. Engage stakeholders, develop methodology and optimization recommendations, and present findings.