ASIC RTL Design Engineer

• RTL design, simulation, and verification for TetraMem ASIC / SoC products
• IP integration and validation
• Understand internal and external requirements, PPA study, RTL coding, implementation, and work with backend team
• Develop reusable internal IPs for AI and/or in-memory computing products
• Support Post-Si testing and validation
• Mentor and coach junior engineers

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
• Experience with Verilog and system Verilog
• Experience with VCS, Verdi or other industry standard tools
• Experience with pre-layout simulation and post-layout simulation
• Understanding of the design flow. Ability to work with the backend team
• Familiarity with AMBA APB AXI Protocol
• Familiarity with RISC/Arm or other core architectures
• Ability to create innovative architecture and solutions to customer requirements
• Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

• FPGA/ASIC design of image processing systems
• Working knowledge of SoC architectures including CPU, GPU or accelerators
• Familiarity with: UVM, place-and-route, STA, EM/IR/Power

All your information will be kept confidential according to EEO guidelines.