Top Tech Jobs & Startup Jobs in Singapore

Validate mixed-signal ICs for low-power, high-performance data center storage. Plan and execute product validation, design and debug test and measurement setups (hardware, software, systems), analyze results, and provide feedback to improve product design and test methodology.

The Epitaxy Fab Assistant operates reactors and testing equipment, performing Epitaxy functions in wafer growth and testing within a fab environment.

Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Plan and perform transistor-to-block-level floorplanning, apply design rules and verification (DRC/LVS/ERC/antenna/EM-IR), and collaborate with senior engineers to adopt methodologies and meet project schedules.

Execute high-quality IC layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes. Manage floorplanning and transistor-to-block layouts, apply advanced process rules, run physical verification, and collaborate across engineering teams to meet project schedules.

Design and produce high-quality digital and memory layout (standard cells, I/O, memories) using Cadence Virtuoso and Calibre/Hercules verification. Apply process-specific layout rules, floorplan and integrate chips, lead reviews, mentor junior engineers, and meet schedule and verification targets.

Design and execute IC layouts for memory, I/O and standard cells using Cadence Virtuoso and verification tools (Calibre, Hercules). Apply process rules for submicron nodes, perform floor-planning, hierarchy layout, physical verification (LVS/DRC/ERC/antenna/EM), integrate chips, document methodology, and deliver quality layouts on schedule while collaborating with the library team.

Design and implement IC layouts for standard cells, memory and I/O using Cadence tools. Perform floorplanning, hierarchical layout and physical verification (LVS/DRC/ERC/Antenna/EM) with Calibre and Hercules. Deliver high-quality layouts on schedule, adopt new methodologies, lead documentation and technology reviews, and mentor junior engineers.

Design and verify high-quality IC layouts for standard cells, memory, and I/O using Cadence Virtuoso and Calibre/Hercules. Apply advanced process rules, floorplanning, hierarchical layout, and physical verification (LVS/DRC/ERC/antenna/emigration). Lead junior engineers, document layout methodology, and meet project timelines independently.

Design and verify high-quality digital and memory layout (standard cell, I/O) using Cadence tools and Calibre/Hercules; perform floorplanning, hierarchy layout, integration, and documentation; lead junior engineers and ensure schedules and process-rule compliance.

Design and verify digital and memory layout for advanced submicron CMOS processes. Apply layout rules, floorplan, complete LVS/DRC/ERC and EM checks, lead junior engineers, and document layout methodology to meet schedule and quality targets.